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bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Removed all synopsys translate_off/on pragmas #689

Closed sifferman closed 2 months ago

sifferman commented 3 months ago

Hello!

According to the IEEE 1364.1-2005 spec 6.3.2, the use of translate_off/translate_on is discouraged as opposed to `ifndef SYNTHESIS. Plus, some newer SystemVerilog frontends such as sv2v, Verible, and PySlint do not have any extra AST support for translate_off, so they may get confused by unsupported unsynthesizable constructs.

Therefore, I changed 200 occurrences of translate_off to `ifndef SYNTHESIS.

I would be happy to hear another perspective if you feel that translate_off is in fact the better option.

Thanks!

dpetrisko commented 3 months ago

Seems reasonable to me. @taylor-bsg

I would suggest to future-proof we use:

ifndef BSG_HIDE_FROM_SYNTHESIS

where in bsg_defines.sv

ifdef SYNTHESIS 'define BSG_HIDE_FROM_SYNTHESIS endif

Which will let us have per-tool logic in the future if we need to

taylor-bsg commented 3 months ago

@sifferman thanks for your contribution Ethan. Would you be able to modify the pull request as suggested by @dpetrisko? @dpetrisko would you be able to verify that BP and bsg_manycore are cool with this?

taylor-bsg commented 3 months ago

@sifferman

sifferman commented 2 months ago

Just made the changes!

taylor-bsg commented 2 months ago

TY!

sifferman commented 2 months ago

Thanks!