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basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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bsg_link FPGA implementation release
#645
gaozihou
closed
1 year ago
6
Release bsg_link FPGA implementation
#644
dpetrisko
closed
1 year ago
0
Update bsg_fsb_node_trace_replay.v
#643
dpetrisko
closed
1 year ago
0
Update bsg_barrier.v
#642
dpetrisko
closed
1 year ago
0
Update bsg_ascii_to_rom.py
#641
dpetrisko
closed
1 year ago
0
Merge testing PRs to master
#640
BrendenPage
closed
1 year ago
0
[bsg_cache] ready_o -> yumi_o
#639
tommydcjung
closed
1 year ago
8
Bsg ready param update
#638
BrendenPage
closed
1 year ago
1
Broken cache testbenches
#637
BrendenPage
opened
1 year ago
5
Bsg mesosync ready handshake update
#636
BrendenPage
closed
1 year ago
0
Bsg cache ready handshake fix
#635
BrendenPage
closed
1 year ago
0
Fixes testbench for bsg_tag
#634
BrendenPage
closed
1 year ago
0
Adds newline to fix lint error
#633
BrendenPage
closed
1 year ago
0
Updates some testbenches for bsg_test
#632
BrendenPage
closed
1 year ago
0
[DO NOT MERGE] Removes deprecated ramulator modules
#631
BrendenPage
closed
11 months ago
3
Updates ready handshake naming signals for bsg_fpu
#630
BrendenPage
closed
1 year ago
0
Bsg misc ready handshake update
#629
BrendenPage
closed
1 year ago
0
Clock gate hard macro for Xilinx Ultrascale
#628
mysoreanoop
closed
1 year ago
1
Bsg noc testbench update
#627
BrendenPage
closed
1 year ago
0
Updates handshaking conventions for bsg_noc
#626
BrendenPage
closed
11 months ago
0
Bsg mem testbench update
#625
BrendenPage
closed
1 year ago
0
Fpu testbench fix
#624
BrendenPage
closed
1 year ago
1
Updates most testbenches for bsg_misc
#623
BrendenPage
closed
1 year ago
0
bsg_nonsynth_dramsim3 failing testbench
#622
dpetrisko
opened
1 year ago
0
Idiv lzc opt
#621
kaamakshee
opened
1 year ago
2
Dramsim3 multiple reads proper fix
#620
dpetrisko
opened
1 year ago
4
Allowing multiple outstanding reads to a single dramsim3 channel to return at …
#619
dpetrisko
closed
1 year ago
0
Add bsg_tag_bitbang
#618
Yuan-Mao
closed
1 year ago
4
Adding burst length input to nonsynth axi mem
#617
dpetrisko
closed
1 year ago
0
bsg_cache_to_test_dram does not support multiple outstanding reads per channel
#616
dpetrisko
opened
1 year ago
1
Clock Mux macro for Ultrascale
#615
mysoreanoop
closed
1 year ago
1
Remove some syntax not supported by the ee477 Cadence flow
#614
derekcom17
closed
1 year ago
0
How can we use a basejump_stl component as a top-level module?
#613
stevenmburns
closed
1 year ago
9
Updates ready handshake naming convention for most of bsg_dataflow
#612
BrendenPage
closed
1 year ago
3
Updates testbenches for bsg_dataflow
#611
BrendenPage
closed
1 year ago
3
(Basejump STL 2.0) Updates bsg_dataflow style and testing infrastructure
#610
BrendenPage
closed
1 year ago
2
Add code for FPGA side of bsg_link
#609
taylor-bsg
opened
1 year ago
2
[WIP] IDIV testbench
#608
dpetrisko
closed
9 months ago
0
[idiv] fix some undeclared and unassigned signals
#607
tommydcjung
closed
1 year ago
2
Adding Verilator Timing Check to bsg_nonsynth_clock_gen
#606
stdavids
closed
1 year ago
0
bsg_cache.v ready_o may be yumi_o
#605
BrendenPage
closed
1 year ago
2
[bsg_cache] fix track_mem_data_r X when word_tracking_p = 0
#604
tommydcjung
closed
1 year ago
4
Refactoring bsg_mem_1rw_sync_xxx_subbanked modules
#603
KinzaQamar
closed
1 year ago
5
Add bsg_fifo_1r1w_rolly, bsg_fifo_1r1w_store_and_forward
#602
Yuan-Mao
opened
1 year ago
1
standardizing harden_p for bsg_mem
#601
dpetrisko
opened
1 year ago
5
Fix fatal syntax
#600
flaviens
closed
1 year ago
2
Add missing commas in bsg_sparse_to_dense_boolean.v
#599
flaviens
closed
1 year ago
0
bsg_comm_link_master_calib_skip_rom.v is broken
#598
flaviens
closed
1 year ago
1
Add missing imports
#597
flaviens
closed
1 year ago
0
Update bsg_link_sdr.v
#596
flaviens
closed
1 year ago
0
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