bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Read/Write ordering in Cache2AXI #654

Closed farzamgl closed 1 year ago

farzamgl commented 1 year ago

This PR adds a CAM-based ordering mode for the cache2axi adapter.

This method issues a read/write fence if there's a pending write/read to the same block address. Requests are cached in a bsg_cam_1r1w_tag_array and are cleared after reading the last word or receiving a write response.