Clock Mux macro for Ultrascale

bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

http://bjump.org/

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Closed mysoreanoop closed 1 year ago

mysoreanoop commented 1 year ago

Tested with 2/3/4:1 muxes with balanced_p and harden_p -- each synthesizes, FPGA-simulates.

dpetrisko commented 1 year ago

LGTM!