bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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bsg_nonsynth_dramsim3 failing testbench #622

Open dpetrisko opened 1 year ago

dpetrisko commented 1 year ago

Before #619 #620, with no additional changes

make -C testing/bsg_test/dramsim3_bandwidth/ tail -n 10 testing/bsg_test/dramsim3_bandwidth/out/unit/simv.log

"testbench.v", 205: testbench.unnamed$$_1: started at 35621500ps failed at 35621500ps
    Offending '(shadow_mem[read_done_col_addr] == dramsim3_data_lo[0][0+:32])'
Fatal: "testbench.v", 205: testbench.unnamed$$_1: at time 35621500 ps
[BSG_FATAL] output does not match expected result for 0x0007c7e0. Expected=00003ff3, Actual=00000000
$finish called from file "testbench.v", line 205.
$finish at simulation time             35621500

619, #620 do not fix