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bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
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Updates testbenches for bsg_dataflow #611

Closed BrendenPage closed 1 year ago

BrendenPage commented 2 years ago

Refactored testbench infrastructure update from https://github.com/bespoke-silicon-group/basejump_stl/pull/610

Summary

Fixes testbenches and makefiles (allows them to compile and run) for all existing dataflow tests.

Adds bsg_dataflow level makefile to run all make commands in directory (for easy syntax verification and directory-level clean commands)

Issue Fixed

Previous infrastructure had not been updated in a number of years, leading to issues regarding compilation from updated module port lists and outdated tooling/non-automated tooling setup in Makefiles

Verification

I have verified that all testbenches are properly run via using make on each subdirectory in testing/bsg_dataflow

bsg_fifo_1r1w_large and bsg_fifo_1r1w_large do not properly finish as they have log file errors I do not understand but the tests themselves run and pass

bsg_parallel_in_serial_out_passthrough_arb and bsg_channel_tunnel fail for reasons unknown but most likely for reasons outside the scope of this PR.

dpetrisko commented 1 year ago

Is this ready to review again?

BrendenPage commented 1 year ago

Is this ready to review again?

Yes! It should be ready to go.

dpetrisko commented 1 year ago

LGTM, merging