bsg_link FPGA implementation release

[gaozihou]

Contains Ultrascale Plus source codes and XDC constraints, and README.

[mxdsgnl]

Are you able to address the use of IOBs and other placement constraints?

Our initial measurements of the board indicate that the IBIS model provided by Xilinx isn't a good match for the real hardware.

from our HyperLynx analysis - these settings should produce a tiny eye that meets LVCMOS logic thresholds:

set_property -dict {PACKAGE_PIN T6 IOSTANDARD SSTL18_I_DCI OUTPUT_IMPEDANCE RDRV_40_40 SLEW FAST} [get_ports {R_BSG_F2A_D[0]}]

In reality we are struggling to keep they eye open at 300MHz.

[mxdsgnl]

The following constraints target cells that don't exist in our design for some reason:

#set_false_path -to [get_cells -hierarchical -filter {NAME =~ main_loop[*].dff_downnode/data_r*}]
#set_false_path -to [get_cells -hierarchical -filter {NAME =~ main_loop[*].dff_upcore/data_r*}]
#set_false_path -to [get_cells -hierarchical -filter {NAME =~ main_loop[*].dff_downcore/data_r*}]
#set_false_path -to [get_cells -hierarchical -filter {NAME =~ main_loop[*].dff_upio/data_r*}]
#set_false_path -to [get_cells -hierarchical -filter {NAME =~ main_loop[*].dff_downio/data_r*}]
#set_false_path -to [get_cells -hierarchical -filter {NAME =~ main_loop[*].dff_tkn/data_r*}]

I have replaced them with "set_max_delay" constraints but I'm not sure that's correct.

Thanks, Nick

[gaozihou]

Hi @mxdsgnl I added example placement constraints as a reference: link to example constraints

Hope these examples are helpful to you!

[taylor-bsg]

@dpetrisko @gaozihou are we ready to merge this?

[dpetrisko]

LGTM, my comments were addressed!

[taylor-bsg]

Thanks everybody, I have merged! @mxdsgnl Paul is going to work on adding some more docs. Please feel free to file github issues with anything that is not clear. If you have source code deltas that are required for Zynq, you can make those changes and do a pull request and Paul can review. We have not done Zynq ourselves yet, but it is on our roadmap.

M