Clock gate hard macro for Xilinx Ultrascale - Githubissues

bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

http://bjump.org/

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Clock gate hard macro for Xilinx Ultrascale #628

Closed mysoreanoop closed 1 year ago

mysoreanoop commented 1 year ago

fixes for bsg_mux (argument reordering)

mysoreanoop commented 1 year ago

Requesting review