The DRAM data return is stored in a PISO and then drained. For some configurations if the core is slow and DRAM is fast, the data can back up in the PISO. If there are multiple outstanding reads, then the PISO can overflow.
Multiple outstanding requests can come from non-blocking caches or a prefetcher for a blocking cache.
The simplest fix is to have a DRAM response data fifo the size of a (parametrized) number of read requests, so that it degenerates to the current hardware for 1 outstanding read request
dpetrisko
commented
1 year ago
The DRAM data return is stored in a PISO and then drained. For some configurations if the core is slow and DRAM is fast, the data can back up in the PISO. If there are multiple outstanding reads, then the PISO can overflow.
Multiple outstanding requests can come from non-blocking caches or a prefetcher for a blocking cache.
The simplest fix is to have a DRAM response data fifo the size of a (parametrized) number of read requests, so that it degenerates to the current hardware for 1 outstanding read request