bespoke-silicon-group / basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog
http://bjump.org/
Other
528 stars 99 forks source link

Add tests for bsg_two_fifo #684

Open OroArmor opened 6 months ago

OroArmor commented 6 months ago

The change in bsg_two_fifo.sv might not be necessary, however I found that without it the head_r and tail_r pointers would no longer be equal, causing an invalid state for the FIFO. https://github.com/bespoke-silicon-group/basejump_stl/blob/9322a573262d17623dfde4689a2e87de915241cb/bsg_dataflow/bsg_two_fifo.sv#L74

I am also curious how to make the allow_enq_deq_on_full_p in bsg_two_fifo_wrapper potentially.sv be something that can be properly parameterized, allowing both the normal and passthrough configurations to be tested.