Only minor changes now that verilator supports timing statements. This PR only fixes basic_32, but would be trivial to port other tests.
resolve blocking / non-blocking mixture in checker. Should all be non-blocking
Add USE_VERILATOR flag to switch between VCS/Verilator
Move to bsg_trace_replay from deprecated bsg_fsb_node_trace_replay
Adding -DWAVE definition to allow sims to be compiled w/wo dump for speed
rename testbench.checker to testbench._checker to avoid keyword conflict (checker is a SV keyword. VCS allows this override but Verilator does not, which is probably the sane thing)
Only minor changes now that verilator supports timing statements. This PR only fixes basic_32, but would be trivial to port other tests.