Closed dpetrisko closed 5 months ago
This PR adds xilinx templates for BRAM inference. This is essential for efficient implementation on FPGA.
TODO: Designate between BRAM and URAM inference for a given width and depth. Currently trusting xilinx
Tested with BP on Vivado 2022.1, correctly infers all 1rw_sync and 1r1w_sync RAMs
dpetrisko
commented
7 months ago dpetrisko
commented
7 months ago
This PR adds xilinx templates for BRAM inference. This is essential for efficient implementation on FPGA.
TODO: Designate between BRAM and URAM inference for a given width and depth. Currently trusting xilinx
Tested with BP on Vivado 2022.1, correctly infers all 1rw_sync and 1r1w_sync RAMs