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### Environment (OS, Python version, PySpice version, simulator)
OS-WIN10 Python-3.6.3 PySpice-1.4.3 simulator-ngspice
### Expected Behaviour
I am trying to build a common simulator for the CMOS …
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There is a spreadsheet @ [GF180MCU (GlobalFoundries 180nm PDK) -- Primitive Model Naming](https://docs.google.com/spreadsheets/d/1G88IhyqXGVu-BgH8hA-_N2YQnNiyPoPEqvXSOzmOaaY/edit#gid=1803291424) which…
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In the irradiance calculation results (`irradiance.html`), we see that the DownScan and UpScan results are shifted by ~0.02nm relative to the reference spectrum (as well as relative to each other). T…
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It would be awesome to see how this CPU would work in ASIC form and Google is offering free tape outs to open source silicon projects on SkyWater's 130nm and GlobalFoundries 180nm MCU process technolo…
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we have just released a fully open source PDK for Globalfoundries 180nm process technology.
The repositories are now available under https://github.com/google - see https://github.com/google?q=glob…
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In TLEF files for any layer a WIREEXTENSION can be set:
```
LAYER MET2
TYPE ROUTING ;
WIDTH 0.28 ;
SPACING 0.28 ;
WIREEXTENSION 0.19 ;
# ...
END MET2
```
This should result…
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One of the other SIMD instruction sets that you may want to consider is RISC-V's vector extension, because it takes a totally different approach than most other common ISAs:
it uses scalable vectors …
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Thanks for making this tool. The latest change sets (Mar 21) solve most of the issues we were seeing, except this one.
We had previously done reg files with latches and multiplexors (in TSMC 180nm…
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### Description
We are working on a design to fabricate with 180nm.
The fab require `274um x 85um` reserved space between IO pads and core area to keep fab structure and silicon number.
In that a…