-
Hi, I am using py-aiger to perform some AIG manipulation.
In particular, I am trying to convert AIG to PySMT formulas.
I have found an example of AIG waking in https://github.com/mvcisback/py-aiger…
-
The `external_aig_solver` command currently assumes an interface that no existing solver supports: AIGER input and DIMACS-style output. The following shell script allows ABC to be used as such a tool,…
atomb updated
1 month ago
-
When the following example code is run with the attached `6s128.aig` circuit from the [HWMCC'17](https://fmv.jku.at/hwmcc17/) dataset,
https://github.com/Ironprop-Stone/python-deepgate/blob/cc91c1f…
-
## Steps to reproduce the issue
using the files from the enclosed zip
[MCVE.zip](https://github.com/YosysHQ/yosys/files/3515572/MCVE.zip)
from the command line run "sby -f MCVE.sby"
Note: as…
-
Running IIMC on the AAG file below (without any parameters) sometimes yields "1" as result, but also sometimes yields:
> iimc: src/mc/ProofAttachment.h:85: void ProofAttachment::setConclusion(int): A…
-
Consider the following MCVE:
```verilog
module mcve2(i_clk, o_v);
input reg i_clk;
output reg o_v;
always @(*)
o_v = 1;
always @(*)
assert(o_v);
endmodule
```
A simple ins…
-
In [SYNTCOMP 2014](http://arxiv.org/abs/1506.08726) and 2015, both input and output formats were in AIGER. There was a unique initial state for the latch variables (all zero, p.5). The inputs `Xu` and…
-
### Version
Yosys 0.38+4 (git sha1 ac0fb2e3011, gcc 14.0.1 -O2 -fexceptions -fstack-protector-strong -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-fra…
-
### Version
0.47 (also 0.40)
### On which OS did this happen?
Linux
### Reproduction Steps
Compile and install yosys 0.40 or yosys 0.47 (I did not try other versions) from the release tarball on …
-
### Version
0.24
### On which OS did this happen?
Linux
### Reproduction Steps
```
module mux (
input wire select_1,
input wire select_0,
input wire in_0,
input wire in_1,
input w…