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Hello,
I have changed the device "LFE5U-12F" to "LFE5U-25F" in cynthion_r1_4.py, set the system variable LUNA_PLATFORM ="cynthion.gateware.platform:CynthionPlatformRev1D4", and have a dry run like…
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Hello, I don't know if I should post the Issue here or on the LiteX repository, after running the following command I get this terminal output:
```
python3 -m litex_boards.targets.radiona_ulx3s --…
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You get messages like:
```
amaranth.hdl._ir.DriverConflict: Bit 0 of I/O port (io-port port_a_5__io__io) used twice, at /home/whitequark/Projects/glasgow/software/.venv/lib/python3.12/site-package…
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It would be useful to have some guidance on preferred usage of the project's new name.
The full title of the project is now "Amaranth HDL", but in most instances within the documentation it is refe…
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The simulations use `.add_sync_process()`, which emits a deprecation warning.
I am very new to Amaranth, so I may be missing something, but `.add_process()` appears to work just fine.
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Repro:
```python3
from amaranth import *
from amaranth.lib import wiring
from amaranth.hdl import Fragment
class Foo(wiring.Component):
def __init__(self, arg):
if not isinsta…
jfng updated
3 months ago
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@antonblanchard just released the vlsiffra project. See the tweet @ https://twitter.com/antonblanchard/status/1580154261962657792
> Introducing https://github.com/antonblanchard/vlsiffra/ - a gene…
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When trying to synthesize a design for the LICL-40, NextPNR-nexus reports `Cell type 'PCLKDIV' instantiated as 'U$$5' is not supported by this device.` despite the primitive being listed on the Lattic…
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The sink Stream in LiteDRAMDMAWriter has the 'ready' flag set by default.
If with_csr is set, shouldn't the 'sink.ready' flag only be set if the 'enable' bit is set in the CSR?
At the moment you…
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With complex bundle types showing up in the arguments of components, it seems that a more general technique to represent IO interfaces is in need. Borrowing ideas from Chisel, I think we can use the c…