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Hello,
I understand that Arty A7 is supported, I want to confirm if Arty S7 need something extra to work.
I follow the build instructions and when loading the gateware on Arty S7 I am getting the …
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Hello. I'm trying to get this working on [Sechzig MX2](https://github.com/machdyne/sechzig), but I get the following error when building:
prjxray.fasm_assembler.FasmLookupError: Segment DB CFG_CENT…
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Hello, we are trying to implement pulpino on Arty a7 35t but it is showing the following error. Can anyone please help us with this?
``````
source pulpino.tcl -notrace
CRITICAL WARNING: [Board 49…
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To reduce the amount of code duplication we should subclass from `litex` platforms' `_io`, `connectors` and methods instead of redefining them. This will prevent surprises and subtle incompatibilities…
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**NOTE:** only 64bits architecture is supported and must support *imafdc*
## InitRAMFS boot
- buildroot/CI: openSBI, soc.dtb, rootfs.cpio. openWRT: Image -> OK
- buildroot/CI: openSBI, soc.dtb. o…
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Hi,
So I've recently tried this on a Rpi4 with the idea to remote debug a Arty-A7 over the network from Vivado 2024.1.2
(since the xilinx tools aren't built for the ARM64)
It does build and run, …
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What a nice demo! But it runs way too fast. The code uses a 12 MHz clock in the constraints, but the current Arty board only mentions a 100 MHz clock. Can you provide a sample xdc file for using the 1…
WD0UG updated
2 years ago
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If this addressed by a PR in flight, just close this.
I'm going through the examples at https://symbiflow-examples.readthedocs.io/en/latest/building-examples.html .
After the counter example is …
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Hello, I am very interested in this project, and I have met some problems in my study.
I have instantiated the `ddr3_x16_phy_cust` and `ddr3_rdcal` modules in your Arty S7-50 project, and programme…
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I follow the following steps to do simulation but cannot get waveform similar to the what's shown in README. Please correct my mistake.
1. Create a vivado project with `xc7s50csga324-1` (arty-s7 bo…