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Are any of the following open-source CPUs targets for powdr?
Specifically, should I ever expect that powdr will run on, say, the Berkeley/SiFive Rocket [rv32ima](https://github.com/chipsalliance/ro…
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`make` succeeded, I was able to generate the .bsv from Target.ml. Some of the bluespec includes seem to no longer exist compared to 2014.01. Any hints on what to do? `RegFileZero` throws an error for …
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Hi,
I find when I compile bluespec to Verilog, I find the functions in bluespec got compiled to verilog modules, but not verilog functions. I'm wondering is there a flag/option to specify compile b…
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**Name:** Bluespec Systemverilog
**URL:** https://github.com/B-Lang-org/bsc
bsv is one of the languages used for hardware development,
Some sample error messages are
```
% bsc -verilog u…
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Hi.
I've been trying to get abc to read my generated [verilog files](https://github.com/iamKarthikBK/sample_design/blob/main/build/hw/verilog/mk_sample_design.v).
I generate these using the [bluespe…
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```
export BLUESPECDIR=/tmp/bsc/inst
/tmp/bsc/util/bluetcl-scripts/expandPorts.tcl foo mkfoo mkfoo.v
couldn't read file "/tmp/bsc/inst/lib/tcllib/bluespec/portUtil.tcl": no such file or directory
…
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`Tutorials/Bluespec_Classic_training/START_HERE.pdf` mentions the following files on slide 8:
- Reference/Lec01_Intro
- Reference/Lec02_Basic_Syntax
- Reference/Lec05_Interfaces_TLM
- Reference/…
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Hi everyone.
I am trying to generate a Verilog files from output bsv files, using the p4fpga/examples, I am working with simple_router example.
I see in the folder p4fpga/examples/simple_router/sa…
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This can be implemented by using a sliding window and a second BAR. The Xilinx Core does not support this feature directly, though. Will use a little Bluespec Module that has one configuration registe…
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### Issue
When using the build option YICES_STUB=1 during building in order to disable Yices, BSC fails to build with error
```
/build/bluespec-git/src/bsc/inst/bin/bsc -stdlib-names -bdir /build…