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**Name:** Bluespec Systemverilog
**URL:** https://github.com/B-Lang-org/bsc
bsv is one of the languages used for hardware development,
Some sample error messages are
```
% bsc -verilog u…
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This issue is where we track the necessary skills required to write and design hardware.
# Bluespec SystemVerilog
- [ ] [Lecture 1](https://www.youtube.com/watch?v=IdTSgYv8PUM)
- [x] Pragnesh…
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`Tutorials/Bluespec_Classic_training/START_HERE.pdf` mentions the following files on slide 8:
- Reference/Lec01_Intro
- Reference/Lec02_Basic_Syntax
- Reference/Lec05_Interfaces_TLM
- Reference/…
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我是做FPGA开发的工作者,初次体验了最新的这个插件,想给出如下建议以及觉得不错的地方:望采纳
1.我觉得那个architecture功能做的不错 可以看到代码的层次结构图,在开发FPGA的时候不用来回的切换vivado界面,比较不错。
2.代码的颜色高亮有点点问题,关键字和变量常量的显示都是蓝色--这个不太具有突出性,我查看的是你里面的fft代码---可以参照插件 Verilog-HDL/S…
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Tracking all logistics here -
**Joining dates**
- [x] Abhijith - 31/05/2019
- [x] Pragnesh - 22/05/2019
- [x] Priyal - 22/05/2019
**Final dates**
- [x] Abhijith - 30/06/2019
- [x] Prag…
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As mentioned in issue #469, there are warnings about non-exhaustive pattern matching in `SystemVerilogScanner.lhs`, in the function [`scanLinePosDirective`](https://github.com/B-Lang-org/bsc/blob/0e9a…
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The Bluespec compiler emits Verilog which makes **[Yosys](https://github.com/yosyshq/yosys)** somewhat unhappy:
```
1.3. Executing Verilog-2005 frontend: /tmp/yosys-bsv-v-QxaOnJ/keccak.v
Parsing …
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[languages.yml](https://github.com/github-linguist/linguist/blob/cddf7476af4c95d1572956ffc5c0cb84f7e431c5/lib/linguist/languages.yml) in the GitHub linguist project has a good list of languages but I'…
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Hi,
I've been trying to use `sqrtFP` from the `FloatingPoint` library, and I was getting incorrect results. I then ran `make check` in `testsuite/bsc.lib/FloatingPoint` (with `testArith = True`) an…
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I've noticed that ppx_deriving_yojson has a far more comprehensive testsuite than the other plugins. I think it might be useful if all the various plugin authors contributed to a shared testsuite tha…