issues
search
Nitcloud
/
Digital-IDE
在vscode上的数字设计开发插件
GNU General Public License v3.0
320
stars
20
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
fix typo
#87
cyrus28214
opened
2 weeks ago
0
用MYHDL生成的VCD文件，用插件查看波形时有问题
#86
xzrsds123
opened
3 months ago
1
未来是否会支持任意形式下全文件夹内的文件都可以解析
#85
miilTgy
opened
5 months ago
0
在插件中使用vivado仿真波形无变化
#84
ziky0827
closed
5 months ago
0
请问是否会加入Vivado TCL自动补全+纠错功能
#83
yuxuan-z19
opened
5 months ago
0
how to deal the command not find
#82
gabiii28
opened
8 months ago
0
仿真时报错error: Unknown module type
#81
firerock1
opened
9 months ago
1
使用生成property.json的命令时，报错找不到这个命令
#80
L-new-H
opened
9 months ago
1
中文README404，仅剩知乎版本
#79
Liber1917
opened
9 months ago
0
找不到修改testbench模板的命令
#78
ycy012
opened
9 months ago
0
宏 误报错
#77
filliam9560
opened
11 months ago
0
I hope to designate the top-level design file within the configuration profile.
#76
qiQWQwww
opened
1 year ago
0
10个月没更新，是关闭项目了吗
#75
wantflyfly
opened
1 year ago
0
使用时自动补全功能消失。
#74
NoNounknow
closed
1 year ago
0
自动例化对于没有写在head的变量不
#73
JWei0703
opened
1 year ago
0
使用generate批量例化的模块层级关系在architecture中无法正确地被识别
#72
Jgfjj
opened
1 year ago
1
Architecture 中无法识别ip文件夹中的ip
#71
Jgfjj
opened
1 year ago
0
关于在多个.v文件的补全
#70
SL8281
opened
1 year ago
0
systemverilog语法识别问题
#69
wantflyfly
closed
1 year ago
1
不支持 .svh 头文件识别？
#68
wantflyfly
closed
1 year ago
1
verilog module 是否支持数组输入？
#67
wanghao815
opened
1 year ago
0
关于Digital的一些建议-望采纳
#66
1391074994
opened
1 year ago
1
‘end else if (condition) begin’ style with error
#65
lydasia
opened
1 year ago
0
未声明的wire reg 可以随意使用等bug
#64
720lhy
opened
1 year ago
1
not a hdlFile
#63
chansonZ
opened
1 year ago
1
VHDL自动补全的问题
#62
xqXQzzz1
opened
1 year ago
0
关于例化模块的异常报错
#61
DreamLand7707
opened
1 year ago
2
在DIDE TOOL界面点击TOOL / FPGA OPTIONS / SOFT OPTIONS 无反应
#60
DreamLand7707
closed
1 year ago
0
Linter not working + Extension debug output missing
#59
MahmoudKMaarouf
opened
1 year ago
1
Option to ignore scanning certain folders for rtl
#58
nitheeshkm
opened
1 year ago
1
"show netlist" option cannot show correctly when other module instantiation in top module
#57
Collect-diamond
opened
1 year ago
2
"PRJ_STRUCTURE": "customer" crushed everything
#56
StrideZhou
opened
1 year ago
1
Can not find moudles that have parameters when instantiate.
#55
DavidZyy
closed
1 year ago
3
建议在索引文件的时候，支持排除路径
#54
joson1
opened
1 year ago
3
关闭GUI后报错，无法识别add_file命令
#53
EriccWuu
opened
2 years ago
5
网站bestduan.github.io失效了？
#52
TurnOffNOD
closed
2 years ago
2
模块里面有递归的话插件就不能正常工作了
#51
hhucchenyixiao
opened
2 years ago
4
Tool commands not found.
#50
Tsegorah1
closed
2 years ago
4
希望支持括号辅助
#49
joson1
closed
2 years ago
6
我的语法检查还是运行不了
#48
soledadsolo
closed
2 years ago
1
Extension causes high cpu load
#47
ritaanthem
opened
2 years ago
1
translate vhdl to vlog
#46
shangyanzhao
opened
2 years ago
2
模块层次树失效
#45
xlsjdjdk
closed
2 years ago
2
Linting功能失效及部分错误
#44
xlsjdjdk
closed
2 years ago
3
自动补全失效
#43
hhucchenyixiao
closed
2 years ago
4
gtkwave 在 vscode 不能打开
#42
hhucchenyixiao
closed
2 years ago
5
状态机预览页面点击“Save as SVG”按钮无反应，无法保存为SVG文件
#41
JeffJiang1024
closed
2 years ago
2
SystemVerilog支持
#40
xlsjdjdk
opened
2 years ago
2
使用generate语句例化时模块层次关系不显示
#39
xlsjdjdk
closed
2 years ago
1
Test Bench 导致溢出
#38
bqsgwys
closed
2 years ago
7
Next