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I've noticed that the volume of channels under the 6581 filter can sound a bit louder in the emulation than on, at least some, real 6581s. This seems to be true regardless of filter response parameter…
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`VS1053_WriteRegister(SPI_CLOCKF,0xB8,0x00); // SC_MULT = x1, SC_ADD= x1`
Because all VS1053 registers are 16-bit the SPI_CLOCKF value is 0xB800=0b1011 1000 0000 0000 where 15..13-bits is clock mul…
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I am troubleshooting an issue on a custom PCB design with the RP2040 and the Winbond W25Q64JVZPIQ part where I am seeing what appear to be occasional bit errors when booting with PICO_FLASH_SPI_CLKDIV…
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Hello,
I was wondering if you can add support for this device:
https://vi.aliexpress.com/i/1005006109579911.html
I have the device and I can be a tester for it but I do not know from where to s…
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Is there any way to reduce the minimum value of parameter DIV_xx_x from 2 to 1?
I try to figure it out, but there still some confused questions like :
Why the minimum value of parameter DIV_xx_x is …
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In the block diagram of the management area of the Caravel, it is mentioned that it has a DLL (https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/_images/block_diagram.png) while in other parts o…
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I saw that the DFLL reference clock is set to 8MHz, but the maximum is 33kHz and so the DFLL will not work in closed loop mode (it will not lock).
Datasheet -> Maximum Peripheral Clock Frequencies ->…
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```
Step 1. What steps will reproduce the problem?
Run i7z on system with 2 sockets with e.g. Intel(R) Xeon(R) CPU E5-2660
Step 2. What version of the product are you using (the download version or…
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```
Step 1. What steps will reproduce the problem?
Run i7z on system with 2 sockets with e.g. Intel(R) Xeon(R) CPU E5-2660
Step 2. What version of the product are you using (the download version or…
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Hello!
Thanks for your great work on this project. And above all on support offered!
I made this project on NodeMCU v3 (esp-12F). Works like intended, except for similar situation than [here](https:…