efabless caravel issues

efabless / caravel

Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

https://caravel-harness.readthedocs.io/

Apache License 2.0

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issues

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Update auto-update-caravel-lite.yml

#557 marwaneltoukhy closed 2 weeks ago
0
Fix #555 full-chip STA: Flatten GL netlist array instances for decaps/fills

#556 amm-efabless opened 4 weeks ago
1
Changed decap_12/fill8/fill4 cell references break downstream full-chip STA (`make caravel-sta`)

#555 amm-efabless opened 4 weeks ago
0
Update Caravan to fix analog IO short

#554 DavidRLindley closed 1 month ago
1
Modifications to reduce poly fill and re-enable LVS.

#553 DavidRLindley closed 2 months ago
0
Changed EF_fill_4_8.mag scale and coordinates

#552 d-m-bailey closed 2 months ago
0
Fixed verilog instance name and ports.

#551 d-m-bailey closed 2 months ago
0
Housekeeping SPI should force `hkspi_disable` to zero on a digital reset.

#550 RTimothyEdwards opened 3 months ago
1
Remove "Google" from copyright notice in Caravel, Caravan, and Openframe. Update version and date.

#549 DavidRLindley opened 4 months ago
0
Caravel: issue with analog routes between user wrapper and pads. Openlane routed thin analog routes to the pad that were strongly coupled to digital signals.

#548 DavidRLindley opened 4 months ago
0
Update Caravel & Caravan to adjust decap fill mix to meet poly density.

#547 DavidRLindley closed 1 month ago
1
Register definition TRM unclear

#546 marwaneltoukhy opened 5 months ago
0
Check for multiple top level cells in final gds

#545 jeffdi closed 1 month ago
2
Check min metal area and space of fill shapes after fill generation

#544 jeffdi opened 6 months ago
0
Added changes for cocotb top testbench for enabling user to add logic to the top level

#543 M0stafaRady opened 6 months ago
0
Ignore comments and add error checking.

#542 d-m-bailey opened 6 months ago
1
Ignore gpio comments and add default value checks.

#541 d-m-bailey closed 6 months ago
1
`make gpio_defaults` incorrectly handles some Verilog constant patterns

#540 amm-efabless opened 6 months ago
2
`make gpio_defaults` can incorrectly parse `user_defines.v` Verilog block comments

#539 amm-efabless opened 6 months ago
1
Delete scripts/tech-files/sky130A_mr.drc

#538 marwaneltoukhy opened 6 months ago
0
Update PLL range with measured values

#537 mole99 opened 6 months ago
0
New TRM document

#536 DavidRLindley closed 7 months ago
0
Tapeout lvs

#535 d-m-bailey opened 7 months ago
0
Formalize a process for updating and releasing the tapeout flow.

#533 DavidRLindley opened 8 months ago
0
add verification for gpio defaults implemented as part of the tapeout flow

#532 jeffdi closed 1 month ago
1
add checks to tapeout flow ensure each of the steps has completed successfully

#531 jeffdi opened 8 months ago
1
reimplement tapeout flow to run with the same code both off and on platform

#530 jeffdi closed 8 months ago
1
Several projects where the defaults block layout was incorrect although it had the same default block numbers.

#529 d-mitch-bailey opened 9 months ago
2
Power-on-reset needs to be robust to late 1.8V supply power-up

#528 RTimothyEdwards opened 9 months ago
0
Update diagrams 3 Examples

#527 azwefabless opened 10 months ago
0
create end-to-end diagram for user design flow through final gds

#526 jeffdi opened 10 months ago
0
85C temperature failure on silicon

#525 marwaneltoukhy opened 10 months ago
0
3.0 Voltage for vddio fails on silicon

#524 marwaneltoukhy opened 10 months ago
3
GPIO low chain pull up and high chain output error on silicon

#523 marwaneltoukhy opened 10 months ago
0
old layouts for defaults used in final layout

#522 jeffdi opened 10 months ago
3
close missing DRC rules in klayout deck

#521 jeffdi closed 1 month ago
15
Bump tj-actions/changed-files from 39 to 41 in /.github/workflows

#520 dependabot[bot] opened 10 months ago
0
include user process for full chip LVS for the ??? shuttle

#519 jeffdi opened 11 months ago
3
Correct user_id bit order in gl verilog and layout.

#518 d-m-bailey closed 10 months ago
1
Corrected the set_user_id.py script to put the bits in the correct direction.

#517 RTimothyEdwards closed 11 months ago
3
mpw-9: user id bits reversed in gl verilog and layout.

#516 d-m-bailey closed 10 months ago
1
Update .readthedocs.yml

#515 marwaneltoukhy closed 1 year ago
0
Revert the user_id_programming.mag file

#514 RTimothyEdwards closed 1 year ago
0
mpw-9f: Save the gds out feedback from make ship/truck/openframe

#513 d-m-bailey opened 1 year ago
0
Update auto-update-caravel-lite.yml

#512 marwaneltoukhy closed 1 year ago
0
Update Makefile

#511 marwaneltoukhy closed 1 year ago
0
update pdk for caravel to reference latest pdk for LVS

#510 jeffdi closed 11 months ago
1
add a CI safeguard to block PR that affect signoff for Caravel

#509 marwaneltoukhy closed 1 year ago
0
Create block_CI.yaml

#508 marwaneltoukhy closed 1 year ago
0
plan for mpw-9f tag for the November shuttle

#507 jeffdi opened 1 year ago
0