-
```mlir
$ cat bar.mlir
hw.module @A(out out_1: i12, out out_2: i12) {
%0 = hw.constant 2: i12
hw.output %0, %0 : i12, i12
}
hw.module @B(out out_1 : i12, out out_2: i12) {
%0 = hw.const…
-
### What component is the issue in?
Front-End
### Which command
- [ ] kompile
- [X] kast
- [ ] krun
- [ ] kprove
- [ ] kprovex
- [ ] ksearch
### What K Version?
v7.1.163
### Operating System
Ma…
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**Summary:** When running circt-opt, I encountered an assertion failure in ExportVerilog.cpp related to handling of a comb::AndOp operation. The tool crashes with the following error:
```
Assertion …
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I have a mmu.sv module for RISC-V implementation:
```Verilog
module mmu #(
parameter integer DEVICE_COUNT = 0
) (
...
output logic [31:2] dev_addr[DEVICE_COUNT]
...
```
that is used in…
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The test MLIR :: mlir-cpu-runner/sgemm-naive-codegen.mlir fails with exit code 2. The failure appears during the execution of the mlir-cpu-runner tool, and the FileCheck command reports an error due t…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
I assign 2 readwrite ports(aka Dual Port in ASIC) in the chisel(as well as the metadata), I tied off the `write…
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Input:
```mlir
scf.if %true {
%true = arith.constant true
}
```
This crashes on release builds, ASAN reports heap-use-after-free. Found via fuzzing.
ASAN report
```
=================…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
Generate verilog for the code below using different values for the last parameter (`ruw`) of the `SyncReadM…
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Would it be possible to have rust-hdl output to circt. https://circt.llvm.org/
One could then use the LLVM/MLIR to optimize the output before outputting System Verilog or VHDL.
For example rust is …
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As in title - the main link to the right is broken, it should be https://circt.llvm.org/
Probably easy to fix but you need admin rights for it :)