issues
search
samitbasu
/
rust-hdl
A framework for writing FPGA firmware using the Rust Programming Language
Other
307
stars
16
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Correct way to drive inputs?
#43
Necromaticon
closed
3 months ago
1
Feature Request: add support for running VHDL/Verilog code alongside/within RustHDL
#42
parker-research
opened
4 months ago
0
Support for Sipeed Tang Nano 9K FPGA Development Board Gowin GW1NR-9 RISC-V HDMI (Tang Nano 9k)
#41
Cr0a3
opened
5 months ago
6
Fix FIR multiplication
#40
dankirkham
opened
6 months ago
0
Generic constants propagate to Verilog output
#39
dankirkham
closed
6 months ago
1
QUESTION: How does array indexing work with non-literal indices?
#38
john-terrell
closed
8 months ago
1
QUESTION: Arithmetic shift right?
#37
john-terrell
closed
8 months ago
1
QUESTION: How to concat bit values together?
#36
john-terrell
closed
8 months ago
1
How does this project works? Any papers or docs?
#35
myrfy001
opened
10 months ago
1
Request: VHDL output
#34
tschinz
opened
10 months ago
0
Support for BeagleV-Fire
#33
jimkring
opened
11 months ago
1
Why rename?
#32
alexpyattaev
opened
11 months ago
0
Dumping BRAM Contents in Simulation
#31
ThePerfectComputer
opened
12 months ago
4
Calling `Simulation::add_testbench` multiple times makes the simulations interfere with each other
#30
PoignardAzur
opened
1 year ago
3
Naming a signal "output" triggers a "custom attribute panicked" error message
#29
PoignardAzur
opened
1 year ago
1
Update svg dependency
#28
PoignardAzur
opened
1 year ago
0
22 incorrect verilog output
#27
samitbasu
closed
1 year ago
1
Use default on LogicState
#26
samitbasu
opened
1 year ago
0
rust-hdl and circt
#25
jcdutton
opened
1 year ago
2
Support match expressions
#24
twitzelbos
opened
1 year ago
0
Support Sum Types
#23
ThePerfectComputer
opened
1 year ago
2
Incorrect Verilog Output
#22
mwbryant
closed
1 year ago
5
surface nextpnr errors during build
#21
kpwebb
opened
1 year ago
1
Document the PWM device
#20
samitbasu
opened
1 year ago
0
Documentation issue
#19
samitbasu
opened
1 year ago
0
Add ICESugar Board Support Package
#18
XxChang
closed
1 year ago
5
13 rework rusthdl docs
#17
samitbasu
closed
1 year ago
0
What's the right way to get `posedge` to appear in this Verilog output?
#16
Boscop
opened
1 year ago
3
Replaced arachne with nextpnr.
#15
samitbasu
closed
1 year ago
0
Add nextpnr-ice40 support for alchitry cu
#14
samitbasu
closed
1 year ago
0
Rework RustHDL docs
#13
samitbasu
closed
1 year ago
0
Support for multidimensional packed bit array
#12
explocion
opened
1 year ago
7
Add documentation
#11
zebreus
opened
1 year ago
3
Fix links
#10
zebreus
closed
1 year ago
0
8 arithmetic shift right not compiling
#9
samitbasu
closed
1 year ago
0
Arithmetic shift right not compiling
#8
john-terrell
closed
1 year ago
2
Logical shift left using Bits<> of different widths doesn't compile
#7
john-terrell
closed
1 year ago
2
2 inline signed conversions dont compile
#6
samitbasu
closed
1 year ago
0
Question about the generated verilog file
#5
AdiwenaPutra
closed
1 year ago
2
Add Fixed point the support to RustHDL. Similar to the support in FIRRTL.
#4
samitbasu
opened
1 year ago
0
Request: Output FIRRTL as well as Verilog
#3
john-terrell
opened
1 year ago
0
Inline signed conversions don't compile.
#2
john-terrell
closed
1 year ago
3
Request: support for enum discriminants
#1
john-terrell
closed
1 year ago
1