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Hi! I found a novel contention-based side channel in Boom, which related to tilelink, described as follows:
In Boom, **L1 icache miss** or **L1 dcache miss** will request data from L2 cache through…
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**Describe the set-up**
* stm32h743iit6
* threadx + usbx
* use USB_OTG_HS as CDC host ,
* USB_OTG_HS dma_enable = ENABLE and enable the dcache
* vscode gcc13.2.0
**Additional context*…
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## 环境
硬件：lpi4a （TH1520）
软件：RevyOS 0721
## 问题描述
在启用了 `-march=rv64gcv` 参数后，遇到了 log 中的错误
> log 过长，放在评论区中
若启用 `-march=rv64gc` 则可以正常跑测试
但目前观测到前两次批次的测试时间差异不大：
第一批次：
- 启用前：1/8 Test #…
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Found in log files of prod system.
```java
java.lang.IllegalStateException: Attribute is not defined: QOS_POLICY
at org.dcache.vehicles.FileAttributes.guard(FileAttributes.java:335)
…
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windows10下，
GNU Emacs 29.4 (build 2, x86_64-w64-mingw32) of 2024-07-05
使用默认的拼音配置，没有出现问题。
```
(require 'pyim)
(require 'pyim-basedict) ; 拼音词库设置，五笔用户 *不需要* 此行设置
(pyim-basedict-enable) ; 拼音词库，五笔用…
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**Is your enhancement proposal related to a problem? Please describe.**
The core r5 (kv260_r5 and related) have the ICACHE and DCACHES, as for TRM. However, zephyr selects CONFIG_DCACHE to N and do…
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I am creating a 3rd party open source dcache implementation and have found that there are missing calls in at least main.c for plugging in a dcache library provider, initializing a dcache provider a…
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Hi, Waujito! Is there any support for old chips like below? Thx for your work!
```
system type : Broadcom BCM5300 chip rev 1 pkg 0
processor : 0
cpu model …
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Since all links are now specified in the topology, we can automatically bounds check messages received on links (mtu, chunk, wmark etc) to make sure they are valid, rather than every tile needing to r…
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Hello @Moschn and @zarubaf
I am working on the write through cache you designed.
I have some questions:
- I would like to reduce the number of way to 2 instead of 8 in default configuration to…