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As issued in the [forsyde-demonstrators](https://github.com/forsyde/forsyde-demonstrators) repository, the generated SDF3 representations are not correct.
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Hi. I find there is also something wrong with multi-dimensional fixed size vector. The simulation in forsyde deep is fine, but the generated VHDL code cannot be simulated.
My code is:
```
{-# …
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Would there be any interest on publishing some or all modules to Maven Central? This issue is somewhat related to #142 .
The use case for such feature is the easy integration of LF tooling into 3r…
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There are plenty of experimental modules which nobody has looked at in a long while, and do not belong to the modeling environment. Some of them might be transferred to [forsyde-shallow-examples](http…
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It might be cool to synthesize some timing diagrams for subsets of LF programs that are driven purely by timers and/or based on execution traces. This idea was stimulated by [PlantUML](https://plantum…
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When running the attached files, `Actor 1` is mapped to both the FPGA and a CPU, while `Actor 2` does not get mapped to anything. I believe this is a typo (it "is" one to each PE in the solution) some…
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When investigating the solution's throughput in e.g. in`body_0_AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticoreAndPL_Orchestratror.json`, there are no values in `process_minimum_throu…
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Hi, I found that the generated VHDL code for 'take' function in Data.Param.FSVec cannot be simulated by writeAndModelsimVHDL. Here is a small example.
```
{-# LANGUAGE TemplateHaskell #-}
module Ta…
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Bold of me to make an issue this early into the project, but I think there might be an issue actually B)
This is the simple code snippet I use
```java
SystemGraph sGraph = new SystemGraph();
…
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In my synchronous application model, one of the actors, SobelSY, is supposed to be mapped to an accelerator tile. To do so, I have set the computational requirements in the ForSyDe IO model of the app…