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Will allow reducing PCIe bandwidth (and higher samplerates in 1T1R PCIe Gen2 X1) and sample processing/copy in SoapySDR.
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devel@pi5-70:~/pico-ice/my-new-pico-ice-firmware/ice_makefile_verilator_counter $ make
/usr/local//bin/yosys -q -p "read_verilog -sv ice40.sv top.sv; synth_ice40 -top ice40 -json gateware.json"
Warn…
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Attempting to use `SoCBusHandler.add_peripheral`, which seems to be a more pleasant name to access the same interface as `SoCBusHandler.add_slave`, chokes in the following way:
```
Traceback (most…
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```
Running Version: 0.4.0
Devices found: 1
Automatically selecting device: LimeSDR-USB, media=USB 2.0, module=FX3, addr=1d50:6108, serial=000908340187342A
Undefined/Failure
Gateware version mism…
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The `ClockGen` module has an off-by-one error when deriving a clock using `.derive` or `.calculate`. The output clock period is one input clock cycle shorter than necessary. This happens only when the…
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# Bug Report
## One-Line Summary
Newer release-7 gateware/firmware fails to initialize Si5324 on Kasli v1.1, reportedly because of an I2C failure.
## Issue Details
We have a Kasli …
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After installing and setting up cynthion on my host control machine, I ran the analyzer before installing Packetry in order to check if it was somehow installed by the previous setup or pip install co…
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Hello,
Have-you already started to work on FPGA verilog/VHDL code?
How to contribute on this project? I've tools and competencies to assemble some prototypes.
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I would like to create gateware that shows what ball of the FPGA goes to what point on the headers.
On each pin, I would like to output a train of pulses, that indicate the ball. First a preamble, …
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I run the mass-storage.py example and then measured the performance using the linux dd command.
Something like this:
`dd if={mounted_device_path e.g. /dev/sdf} of=/dev/null bs=512 count=100000`
T…