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**Bug**
I tried to run the benchmarks on gem5 with KVM acceleration, cause without `CPUTypes.KVM` the simulation appears to be extremely slow. All the benchmarks seems to perform well at the beginnin…
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**Describe the bug**
Gem5 cannot set the locale to `C.UTF-8`, gem5 appears to only support `C` locale, and also defaults to it, while native hardware appears to default to `C.UTF-8`.
**Affects ver…
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Hi.
Thank you for making Penglai open-source. It is a great work!
In the OSDI paper you mention that Penglai (as well as SIT and VAULT) has been implemented in the Gem5 simulator. Would you know…
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Hi! I really like the idea of your benchmark. I have been using the original RIPE benchmark but it does not work well with the x86 version of gem5. I wanted to use a RISC-V version that does not need …
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环境描述：
GEM5：xs-dev f231aa596b60bb096a0892fbfc4d68dc713d000f
NEMU：master cf24515c85f5be898687959ab299ea276dbd7c56
DRAMsim3：master 29817593b3389f1337235d63cac515024ab8fd6e
[LibCheckpointAlpha](http…
rmxpf updated
3 weeks ago
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**Describe the bug**
When using 8 RISCV ATOMIC CPUs to boot up a 24.04 ubuntu disk image created by following the [riscv-fs](https://github.com/gem5/gem5-resources/tree/stable/src/riscv-fs/riscv-ubun…
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**Describe the bug**
The execution result of the riscv vector slide instruction is not as expected. The picture of trace here shows the bug. (vlen=128)
The results in trace do not conform to the d…
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I want to test out the integration with gem5 as described in the fast18 paper. However, I cannot find any hint in the code or documentation as to where I should start. Is this functionality present in…
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**Describe the bug**
gem5 crashes with panic 'Unrecognized/invalid instruction executed' on X86 when executing `avx2` instructions.
**Affects version**
gem5 version DEVELOP-FOR-24.1
gem5 co…
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Hi,
Thanks for contributing such a great tool. I had a problem when compiling gem5_astra with scons. A module named 'jobfile' is missing. I tried to update the dependencies used in original Gem5 si…