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您好,我下载了这个工程在执行第一个step的时候出现了jtag0 faild的问题,错误信息为:
jtag0: Failed to bind socket: Address already in use (98)
jtag0: Unable to create TCP server on port 44853
情况如下图:
![11](https://github.com/chen…
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Hello,
Have you had the chance to implement JTAG ? I tried using a ESP-PROG, connected to IO12, IO14 and IO15. I then connected to IO13 directly on the ESP module and removed R37. I tried with Plat…
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When I try to connect to the core using JTAG, I can detect the version of RISC-V, but I cannot use CPU halted, which leads to a connection failure. How can I resolve this issue?
![微信图片_20240517114251…
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JTAG mode does not work with stlink. Check if swapping TDI with TDO works.
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Has anyone had any success getting JTAG working?
I've got the sipeed SLOGIC and setup the pinmux for JTAG, but it can't be detected....
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While `embassy_usb_serial_jtag` works - `usb_serial_jtag` doesn't work for me. Tested on ESP32-S3, ESP32-C3, ESP32-C6 ... all the same.
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Hello everyone,
I want to know which kind of JTAG debugger is supported on VCU118 board.
Xilinx internal JTAG chain via the bscane2 primitive or external JTAG debugger?
Is any changes needed on fpg…
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With the automation provided by JusTAG, we're very close to being able to do push-button updates to the register map (i.e., edit markdown files and regenerate the JTAG implementation.) However, there…
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I have some code that happens to work with questa and xilinix vivado, but it just does not work with verilator, and the error message seems misleading, however the code is long so I removed a big chun…
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Hello,
I've created init and .bat file to use with the digilent HS2 jtag, attached in the zip
[HS2.zip](https://github.com/user-attachments/files/16183572/HS2.zip)