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**Is your enhancement proposal related to a problem? Please describe.**
Our system is an RT1170 combined with a Lattice Crosslink NX FPGA. No external RAM.
This means our system has 1MB RAM. Howev…
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**Describe the bug**
When multiple ICE40 instances on the same SPI master are enabled the build will fail, as there will be multiple instances of the same pinctrl-config object within fpga_ice40.c.
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Title. Why? Because I wanted to see how the OrangeCrab performs: https://store.groupgets.com/products/orangecrab
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thanks a lot for this extension and the tutorials around the tang nano 9k ! its been super helpful getting started with fpga stuff for me.
im now trying to program a [icesugar-nano](https://github.…
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Theres both the xilinx Zynq soc with it's integrated FPGA (usually referred to as "the" rio FPGA), and the Lattice MachXO2-640. Neither of these have easy qemu support but i found https://www.xilinx.c…
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In case of a bitstream for a wrong FPGA I get the error message
`OSError: Configuration failed: part ID mismatch / (04a00e10)`
It seems to be [generated here](https://github.com/greatscottgadgets/ap…
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Would be great to support key programming for the Lattice ECP5 (key is OTP and non-volatile).
In [ECP5 FPGA-TN-02202-1.7 ](https://www.latticesemi.com/view_document?document_id=39450) are some info…
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Hi, Sir;
May I get an FPGA board/Xilink from your support to verify the code in FPGA/Xlink Board?
Or I could upload your code into the Lattice FPGA board such as model No. is LIFCL-40-VIP-SI-PC…
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With Lattice ECP5-25F FPGA used by OrangeCrab, $readmemh does not actually initialize an array element.
Also, attempting to manually initialize an array element beyond its number of elements, passe…
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I have Xilinx Kintex XC7K325 board and ECP5 color light 75b board and openFPGALoader works fine with ft2232 cable. However, I am not able to load the bitstream using CH347. I tried both Xilinx and Lat…