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This ticket is only for simulator & witgen tasks. There is a follow-up task for circuit/constraining: https://github.com/AztecProtocol/aztec-packages/issues/9457
## Simulator tasks
These will be cha…
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### The problem you're addressing (if any)
Current fan control settings provided by the IT8659 (in protectli vp66 series) do not allow for a 0rpm setting, it would be nice if such option was added …
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https://github.com/ed255/riscu-jolt/issues/4 concerns only on implementing the instructions which most of the time receive some inputs (as registers) and calculate some outputs (as registers).
To v…
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**Describe the bug**
After parsing a quantum circuit written in OpenQASM 3.0 using the BraketSimulator, the conditional instructions (specifically the `if` statement and the `x` gate) are not include…
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The "Digital" logic simulator, right here on Github : https://github.com/hneemann/Digital
Can directly produce JED files for burning into a PAL/GAL chip.
You can use the Analysis->Synthesis menu…
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Hello you have a neat little app and I like it very much but i would like to request a feature. In the past I have used a lookalike application called 'Logic Circuit Simulator' and it has a feature w…
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This is a design proposal and tracking issue for the implementation of the Handshake-level dataflow circuit simulator, or *Handshake simulator* for short. While we already have an experimental version…
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i've spent a bit of time recently approaching our qcvv library as a user. High level reaction: it's really quite nice, and genuinely makes life easier when implementing/experimenting with qcvv routine…
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**Is your feature request related to a problem? Please describe.**
I'm currently using Xarrows in a logic circuit simulator as the connections between components. I'm using grid pattern for a more …
Aurux updated
4 months ago
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One issue with L-E (and the original Logisim) is that it will not uncover possible timing issues in a circuit, since every component in the circuit has the same propagation delay.
When simulating a c…