EPFL-LAP dynamatic issues

EPFL-LAP / dynamatic

DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

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issues

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[Handshake] Unify MC/LSQ memory ports

#193 lucas-rami opened 2 days ago
4
[build.sh] Expose LLVM's parallel link job throttling.

#192 schilkp closed 4 days ago
1
[Handshake] Adding completion signals to store operations

#191 rpirayadi opened 5 days ago
5
Fix the bug in how UnbundleOp is printed

#190 rpirayadi closed 5 days ago
0
[docs] ninja check-dynamatic behavior documentation

#189 ebosnjak closed 5 days ago
0
[hls-verifier] Fixed brace style inconsistencies

#188 ebosnjak closed 1 day ago
0
[Experimental][Analysis] GSA Analysis

#187 pcineverdies closed 1 week ago
1
[Analysis] Control Dependence Analysis

#186 pcineverdies closed 4 days ago
6
[Handshake] Postponing the connection of memory operations to LSQ or Memory Controller

#185 rpirayadi opened 2 weeks ago
14
[integration-test] Add origin file for admm

#184 murphe67 closed 2 weeks ago
0
Compilation Error with Resource Sharing: C Program with Function Calls

#183 udareechk opened 2 weeks ago
1
[Speculation] ctrlSignal for commit units at both sides of a branch

#182 shundroid opened 2 weeks ago
0
New routeCommitCtrl algorithm

#181 shundroid opened 2 weeks ago
6
[Verilog] Fix syntax error in select.v

#180 schilkp closed 2 weeks ago
0
[hls-verifier] Fixed bug where IEEE754 NaN values were incorrectly compared

#179 ebosnjak closed 3 weeks ago
1
[export-dot] No Specific Identifiers in Module Labels

#178 cosmiclat05 closed 3 weeks ago
1
Implementation of Fast Token Delivery flow within Dynamatic

#177 pcineverdies opened 1 month ago
14
Updating PassCreation tutorial to fit the new version of dynamatic

#176 rpirayadi closed 1 month ago
0
[Buffers] Introduce New Buffering Algorithm & Fixing Consistency Issue in Existing Buffering Algorithm

#175 QinYuan2000 opened 1 month ago
0
[Speculation] SaveCommit units don't handle NoCmp signal correctly

#174 shundroid opened 1 month ago
1
[Speculation] Ready bit of the speculator's signals are always 1, causing bug when predecessor stalls

#173 shundroid opened 1 month ago
1
Supported speculation in the current backend

#172 shundroid opened 1 month ago
5
[VHDL/Backend] Incompatible signal types for 1-bit address

#171 Jiahui17 opened 1 month ago
5
[SpeculationPass] Fixed SCCommitCtrl connection

#170 shundroid closed 3 weeks ago
8
Rename signals and ops relevant to save-commit units

#169 shundroid opened 1 month ago
0
[SpeculationPass] Fixed the enable signal of speculator

#168 shundroid closed 1 week ago
13
[HDL] Remove the TEHB from Mux

#167 Jiahui17 opened 1 month ago
0
Using the bash script to test Resource Sharing: Simulation Error for float_basic.c

#166 udareechk closed 1 month ago
10
Failed to export RTL (vhdl) with exp-sharing-wrapper-generator

#165 udareechk closed 1 month ago
3
[MLIR] [LLVM] ninja check-dynamatic failed

#164 PigBrainOverflow opened 1 month ago
2
[VM] Ubuntu-based Virtual Machine Link for DYNAMATIC is Inaccessible

#163 SubZeroArt closed 1 month ago
1
[ForceMemoryInterface] fix attribute setting logic.

#162 Jiahui17 closed 1 month ago
1
Casting floats to double issue

#161 murphe67 closed 13 hours ago
4
[integration-test] Add ADMM integration test

#160 murphe67 closed 1 month ago
4
[RTL] fixed control_merge.vhd

#159 shundroid closed 1 month ago
1
Fixed HandshakeSpeculationPass

#158 shundroid closed 1 month ago
0
[HandshakeOptimizeBitwidths] Optimize width of address-carrying channels

#157 lucas-rami closed 1 month ago
1
[Frontend] Buffer placement option in the compile command

#156 Jiahui17 closed 1 month ago
2
[Bitwidth] Array indices are always inefficiently set to 32-bit

#155 Jiahui17 closed 1 month ago
6
Exception during compile command on Introduction/Ch1

#154 leothaud closed 1 month ago
2
[HDL] Unit tests of VHDL/Verilog dataflow units

#153 Jiahui17 opened 2 months ago
0
[Handshake] Branch Canonicalization

#152 kb29x37 opened 2 months ago
3
[build] HandshakeOps.cpp and CfToHandshake.cpp failed to build with clang-7.0

#151 Jiahui17 closed 1 month ago
1
[HDL] Fixing reset in mem_controller_loadless{.v,.vhd}

#150 Jiahui17 closed 2 months ago
0
[Verilog] Control merge Verilog module not synthesizable

#149 Jiahui17 opened 2 months ago
0
[Handshake] Add canonicalization patterns and folders

#148 lucas-rami opened 2 months ago
0
[Support] Shannon expansion in Boolean Logic library

#147 pcineverdies closed 3 weeks ago
8
[RTL] Fix in `join_handshake`

#146 pcineverdies closed 2 months ago
1
[TimingModels] fix timing model library and retrieve logic

#145 Jiahui17 closed 2 months ago
0
[External functions] Updated the external function feature

#144 Carmine50 closed 2 months ago
5