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I have found a bug in SDK v2.6.0 at zephyr/drivers/flash/nrf_qspi_nor.c while erasing the external MX25R64 flash.
**Environment:**
* nRF5340 DK Hardware (MX25R64 external flash over QSPI with no…
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**Describe the bug**
I am trying to get the [LittleFS sample](https://github.com/zephyrproject-rtos/zephyr/tree/main/samples/subsys/fs/littlefs) to run with an external qspi flash W25Q128FV on my nuc…
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Schematic diagram
[jc3636w518.zip](https://github.com/user-attachments/files/16201959/jc3636w518.zip)
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QSPI in H7 uses MDMA, which `embassy` or `embassy_stm32` not yet implemented.
Solution is to implement MDMA support in `stm32-data` and `embassy_stm32::dma`.
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Thank you for shared impressive project. I want to used wifi 2.4G/5G , the only esp32c5 compatible.So, I used the esp32-p4 chip for mcu host , and esp32c5 via sdio connected to esp32-p4 sdio port. How…
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### Version
_No response_
### Describe the bug
w25qxx_set_status2() and w25qxx_set_status3() functions perform the check (after the write) always on Status Register 1 (W25QXX_COMMAND_READ_STATUS_RE…
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This is dependent on a register API for the FPGA's QSPI Flash controller which will be forthcoming.
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**Many thanks to Tobozo for setting up this new panel for me.**
Running the code below gives this error in `tft.init();` -
` E (1006) spi_master: spi_master_init_driver(236): invalid core id`
Using…
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Hoping to take advantage of the QSPI and DMA features of the SPI peripheral. This is listed as TODO in spi.rs
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Hi @Nitsirks , @calebofearth ,
We have encountered a testcase hang when RISCV core tried to access UART/QSPI registers, due to below tie-offs in caliptra top. We have not defined CALIPTRA_INTERNAL_…