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Run bin/covergroupgen.py
Look at No template found messages
Please look at your test plans and either fix typos or add missing templates.
UET
***** Writing rv64/RV64ZcaZicsr_coverage.svh
No tem…
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There are a few places I've noticed where the existence of bitfields depends on `xlen`. For example in `Mstatus`:
```
bitfield Mstatus : xlenbits = {
// The MBE and SBE fields are in mstatus in…
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@aswaterman As I was going through the `encoding.h` file, I observed that B-extensions are not present. It may be probably because the files with prefixes `rv32_zb*` (e.g., `rv32_zbb`, `rv32_zbs`) a…
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Do you think it's feasible to make a tool for valgrind to convert RV32 code to RV64 on the fly?
e.g. see `slli` or `c.slli`, pretend you saw `slliw`, etc.
It seems that if you want to simply run…
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With ISS as one abstraction level option in Wireguard-FPGA [sim TB](https://github.com/chili-chips-ba/wireguard-fpga?tab=readme-ov-file#simulation-test-bench), we are looking for it to be timing-aware…
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I think we should switch from Make to CMake. This would have a number of benefits:
1. We can easily make the arch part of the targets instead of a Make parameter. I.e. instead of
```
ARCH=RV32 …
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# Official Test suite
[RISC-V Tests](https://github.com/riscv-software-src/riscv-tests)
## How to setup *Linux only*
[Prerequisites](https://github.com/riscv-collab/riscv-gnu-toolchain/blob/master/…
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Prebuilt binary of Sail doesn't exist.
I was running test on Macbook M1, commit `164da62b64fa050569b22910ea207525884802ba`.
```
$make arch-test
CC build/map.o
CC build/utils.o
CC …
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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Chipyard now supports simulating two different vector units:
- Saturn (https://github.com/ucb-bar/saturn-vectors) supports full 1.0 RVV, with virtual memory, precise traps, and Zvfh/Zvbb
- Ara (ht…