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# Official Test suite
[RISC-V Tests](https://github.com/riscv-software-src/riscv-tests)
## How to setup *Linux only*
[Prerequisites](https://github.com/riscv-collab/riscv-gnu-toolchain/blob/master/…
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Hi!
The unprivileged specification version 20240411 states that:
> Any AMO can be emulated by an LR/SC pair
Is this with exception of AMOCAS.D for RV32? Since:
> An SC can only pair with the m…
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We have SCMODE but no way to extract it back out. For RV64 one could slice it out of the high bits, but this gets rather ugly on RV32.
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the RV32/64G instruction set listing chapter is a really handy summary for those of us who have to work on assemblers/disassemblers/emulators. recent versions of the spec are a great improvement in te…
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### Board
ESP32-C6
### Device Description
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### Hardware Configuration
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### Version
v3.0.2
### IDE Name
Arduino IDE and VSCode
### Operating System
Fedora 39
### F…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
According to RISC-V ISA specification, for RV32, the bit 25 of instructions `BCLRI`, `B…
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The xtheadfmemidx doc says "All instructions are available for RV32 and RV64". But th.flurw seems identical to th.flrw on RV32.
I found this patch that removed some of the "u" instructions from RV3…
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Some instructions have different encodings between RV32 and RV64.
From the RISC-V ISA Specification (20191213), Chapter 24, "RV32I Base Instruction Set":
![image](https://github.com/ThinkOpenly/sa…
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### The issue
- Running riscv32 userland with riscv64 kernel is broken
### Steps to reproduce
- Use those firmware/kernel/rootfs: [rv32_umode.zip](https://github.com/LekKit/RVVM/files/14801669/rv…
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When I ran:
make ARCH=RV32
echo "declare {isabelle} rename field sync_exception_ext = sync_exception_ext_exception" >> generated_definitions/lem/RV32/riscv_types.lem
lem -isa -outdir generated_de…