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sail-riscv
Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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How to generate a reference ISA model in SystemVerilog?
#503
SeddonShen
opened
6 hours ago
0
Update README.md based on updated makefile
#502
jordancarlin
closed
5 days ago
2
Use physical addresses for LR/SC reservations
#501
Timmmm
opened
1 week ago
1
Remove `etc` directory
#500
AbhinavMir
closed
4 days ago
3
Fix consecutive builds of the OCaml emulator
#499
Timmmm
closed
1 week ago
2
Increase TLB size to 64
#498
Timmmm
opened
1 week ago
2
Remove redundant CSR privilege checks
#497
Timmmm
opened
1 week ago
1
Fix TLB bug with zeroed upper bits
#496
Timmmm
opened
1 week ago
1
Refactor `haveExt()` & `sys_enable_ext()` functions
#495
Timmmm
opened
2 weeks ago
3
Implementing callbacks in sail-riscv for state-changing events
#494
kseniadobrovolskaya
opened
2 weeks ago
5
Upgrade the build process via GitHub Actions
#493
rpsene
opened
2 weeks ago
19
help with compiler error
#492
ved-rivos
closed
1 month ago
4
Add unratified Smctr and Ssctr extensions
#491
ved-rivos
opened
1 month ago
1
zilsd/zcmlsd Support
#490
simonacostinescu
opened
1 month ago
0
`vsetvli` vector tail agnostic and vector mask agnostic operands are mandatory
#489
ThinkOpenly
opened
1 month ago
7
Use multiple threads for LTO
#488
Mudassir10X
closed
3 weeks ago
3
Sail-riscv uses only 1 cpu thread at a time thus slowing down the compilaton.
#487
Mudassir10X
closed
3 weeks ago
0
Sdtrig support
#486
Mudassir10X
opened
1 month ago
9
Store conditional speculative failures can happen too early
#485
Timmmm
opened
1 month ago
0
Update bitfield syntax
#484
jordancarlin
closed
1 month ago
1
csim: Fix C23 compatability warning
#483
Alasdair
closed
1 month ago
1
Fix riscv_insts_mext whitespace introduced in #480
#482
jordancarlin
closed
1 month ago
1
Sail Crosscheck Testing with ACT Against Spike
#481
Abdulwadoodd
opened
1 month ago
6
Move haveMulDiv() guard to encdec for M extension
#480
jordancarlin
closed
1 month ago
1
Remove unused (f)reg_name_abi functions
#479
jordancarlin
closed
1 month ago
4
Remove effect annotation in vext_vset
#478
jordancarlin
closed
1 month ago
1
Remove unnecessary matches for loads/stores
#477
Timmmm
closed
3 weeks ago
7
Minor style fixes
#476
Timmmm
closed
1 month ago
1
Add some missing explicit var declarations
#475
Timmmm
closed
1 month ago
2
Handle 34-bit PMP address overflow
#474
Timmmm
closed
1 month ago
1
Remove duplicate type declarations for mem_read
#473
Timmmm
closed
1 month ago
1
Replace some bits(12)s with csreg
#472
Timmmm
closed
1 month ago
1
Check misalignment of AMOs before address translation
#471
Timmmm
closed
2 weeks ago
2
Use bool <-> bit mappings from riscv_types.sail
#470
Timmmm
opened
1 month ago
3
Move haveAtomics() guard for atomic instructions to guard clauses
#469
Timmmm
closed
1 month ago
1
Change ext_data_get_addr to use bytes for width
#468
Timmmm
closed
3 weeks ago
1
Handle address translation for misaligned loads and stores better
#467
Alasdair
opened
1 month ago
16
Refactor MUL instruction
#466
Alasdair
closed
1 month ago
2
Replace vmandnot and vmornot with vmandn and vmorn - Issue #421
#465
ShivangMishra
closed
1 month ago
6
Remove theorem prover targets from default Makefile rule
#464
Alasdair
closed
1 month ago
2
Add Svinval extension.
#463
martinberger
closed
1 month ago
7
Add Svinval extension.
#462
martinberger
closed
2 months ago
3
Don't read or write 8 bytes for 4-byte PTEs
#461
Timmmm
closed
1 month ago
8
Remove trailing whitespace in README
#460
Alasdair
closed
2 months ago
1
VM code reads 8 bytes even for 4-byte PTEs
#459
Timmmm
closed
1 month ago
2
RVWMO support via Sail concurrency interface
#458
Alasdair
closed
1 month ago
1
VM code doesn't check reserved bits of PTEs are zero
#457
Timmmm
opened
2 months ago
5
fix disassembly problems
#456
KotorinMinami
closed
1 month ago
6
Implement Zicbom, Zicboz (cbo.flush, cbo.inval, cbo.zero)
#455
Timmmm
opened
2 months ago
3
Added pmm Support
#454
HAMZA-AFZAL404
opened
2 months ago
0
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