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sail-riscv
Sail RISC-V model
https://lists.riscv.org/g/tech-golden-model
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Remove vector of bools in vext
#622
rez5427
opened
1 day ago
1
Fix bits SEIP, STIP, and SSIP of mip and SEIE, STIE, and SSIE of mie read-only problem
#621
KotorinMinami
closed
2 days ago
4
fix: Print MTI value upon hart update for machine timer interrupt visibility
#620
Ali-Faraz-10xe
opened
4 days ago
5
Fix mstatus legalisation of SD bit
#619
Timmmm
closed
4 days ago
2
Remove pc alignment mask
#618
rez5427
opened
6 days ago
11
Use newtypes for register indices and numbers
#617
nwf
opened
1 week ago
1
Simplify getPendingSet() interrupt handling
#616
Timmmm
opened
1 week ago
0
use newtype to reflect address type
#615
KotorinMinami
opened
1 week ago
2
Improve `to_bits` type checking
#614
Timmmm
opened
2 weeks ago
1
Fix delegated interrupt handling
#613
Timmmm
closed
1 week ago
6
Hypervisor extension
#612
defermelowie
opened
2 weeks ago
0
Zero mstatus.UPIE/UIE bits in legalize_mstatus
#611
Timmmm
closed
2 weeks ago
2
Zcmp ext
#610
rez5427
opened
3 weeks ago
2
The definition of the function is_aligned_addr overlaps with the function is_aligned
#609
KotorinMinami
opened
3 weeks ago
4
Make calculate new vl configurable
#608
rez5427
opened
3 weeks ago
2
Remove vlenb register
#607
rez5427
closed
3 weeks ago
4
remove function sys_enable_next
#606
KotorinMinami
closed
1 month ago
2
Add parameter name to sys_vector_vlen_exp and sys_vector_elen_exp
#605
jordancarlin
closed
1 month ago
6
Add Zfhmin support
#604
jordancarlin
closed
3 weeks ago
3
Separate Zifencei extension from base ISA
#603
jordancarlin
closed
1 month ago
1
Documentation Updates: reorder README and combine with STATUS.md
#602
jordancarlin
closed
3 weeks ago
2
Added support of Smepmp
#601
KotorinMinami
opened
1 month ago
2
Merging more with updates
#600
jordancarlin
closed
2 weeks ago
2
Rename ext_write_fcsr
#599
jordancarlin
closed
1 month ago
1
Replace zero_extend(0b0) with zeros()
#598
Timmmm
closed
1 month ago
1
Refactor chip reset
#597
Timmmm
opened
1 month ago
1
Move Sail exception code into its own file
#596
Timmmm
closed
3 weeks ago
1
Add menvcfgh to csr_name_map
#595
Timmmm
closed
1 month ago
1
Fix RV64F compilation, simplify fmv implementation, and make nan boxing functions generic
#594
Timmmm
closed
1 week ago
7
Various issues around clearing the bottom bits of xepc
#593
Timmmm
opened
1 month ago
1
Move scattered CSRs
#592
jordancarlin
closed
1 week ago
10
Remove files upstreamed to Sail 0.18
#591
jordancarlin
closed
1 month ago
2
Make VLEN and ELEN configurable and remove registers
#590
rez5427
closed
1 month ago
6
Unnecessary Vector/FP Extension Dependency
#589
JosephMoore25
opened
1 month ago
7
PMP NA4 Region Upper address calculation updated
#588
MuhammadHammad001
closed
1 month ago
1
NA4 Region not calculated correctly
#587
MuhammadHammad001
closed
1 month ago
4
Merge with updates
#586
rez5427
closed
1 month ago
2
Saturation remove set 0
#585
rez5427
closed
1 month ago
4
Remove N extension
#584
Timmmm
closed
1 month ago
6
Merge 'with' updates
#583
Timmmm
closed
2 weeks ago
2
Replace zero_extend(0b0) with zeros()
#582
Timmmm
closed
1 month ago
0
Change sign to unsign in v extension
#581
rez5427
closed
1 month ago
3
Update Linux images
#580
Timmmm
opened
1 month ago
1
Confusing assembly clause : VSUXSEGTYPE
#579
moste00
closed
1 month ago
2
Update Makefile about riscv.smt_model
#578
westtide
closed
1 month ago
2
fix some typo in v ext
#577
rez5427
closed
1 month ago
13
Outdated Status.md file
#576
jordancarlin
closed
3 weeks ago
2
Remove old Sail workaround for Virtual Memory params
#575
jordancarlin
closed
1 month ago
1
Redundant ext_write_CSR clauses for read-only vector registers
#574
Timmmm
closed
3 weeks ago
0
Add Debug Native Trigger Support
#573
YazanHussnain-10x
opened
1 month ago
9
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