-
Run bin/covergroupgen.py
Look at No template found messages
Please look at your test plans and either fix typos or add missing templates.
UET
***** Writing rv64/RV64ZcaZicsr_coverage.svh
No tem…
-
Chipyard now supports simulating two different vector units:
- Saturn (https://github.com/ucb-bar/saturn-vectors) supports full 1.0 RVV, with virtual memory, precise traps, and Zvfh/Zvbb
- Ara (ht…
-
Jolt can theoretically support 64-bit word sizes with relative ease. We would like to evaluate the extent to which RV64 would be more efficient than RV32 for certain programs. For example, we expect R…
-
Make sim is giving error, if two extensions have same instructions. But as suggested in the 000_RISCV_summary-bitmanip_amo.pdf
"Zknd and Zkne (RV64 only): AES Key Schedule" has the same Instruction…
-
The following program miscompiles when using clang++ for rv64:
```
$ cat foo.cpp
#include
int main() {
long double y = NAN;
_Float16 a = static_cast(y);
return (a != a);
}
```
The …
-
64bit apps are very likely to have a different needs.
RV32 only ext can recycle OP-32 and OP-IMM-32
-
Privide a ready-make config for GitHub codespace, this could help beginners participate in ACT.
- This can help them immediately start their work, like running a "hello world" of riscof
- unified-…
-
There are a few places I've noticed where the existence of bitfields depends on `xlen`. For example in `Mstatus`:
```
bitfield Mstatus : xlenbits = {
// The MBE and SBE fields are in mstatus in…
-
Do you think it's feasible to make a tool for valgrind to convert RV32 code to RV64 on the fly?
e.g. see `slli` or `c.slli`, pretend you saw `slliw`, etc.
It seems that if you want to simply run…
-
The following code compiles:
```llvm
source_filename = "example.925e6eb0586113f0-cgu.0"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu…