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for the line 221-244 in the file `rvv-rollback.py` :
```python
case 'vsetivli':
fractional_LMUL = ["mf2", "mf4", "mf8"]
if any(fLMUL in line for fLM…
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Notation note links that point to internal pages don't seem to be working - found examples here:
https://www.mechref.org/sta/cartesian_coordinates/?origin=sidebar
https://www.mechref.org/dyn/vec…
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**Describe the bug**
I'm trying to test [vector instructions](https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc), but it seems to give me error saying zephyr is unable to rec…
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If use fixed vector types to be parameters in inline asm for risc-v, I'll get the error information,
`error: couldn't allocate output register for constraint 'vr'`
The test code as follows:
```…
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Hello，
I tried to enbale the JIT of mozjs115 by setting `CONFIGURE_FLAGS += --enable-jit` in `debian/rules`
However, after making this change, there is 390 failures reported.
Could you provide so…
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It is currently completely missing.
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# Summary
|New Failures|gcc|g++|gfortran|Previous Hash|
|---|---|---|---|---|
|linux: RVA23U64 profile lp64d medlow multilib |272/8|0/0|0/0|[086ee8d08669fe597e6c63a4e5489d2df7698ec8](https://github.c…
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/opt/llm/InferLLM/src/kern/optimized/rvv/kernel.cpp: Assembler messages:
/opt/llm/InferLLM/src/kern/optimized/rvv/kernel.cpp:155: Error: unrecognized opcode `vsetivli x0,1,e32,m1', extension `v' or `…
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Hi @rdolbeau
We’ve recently been using your risc-v optimized fftw3 implementation found in https://github.com/rdolbeau/fftw3/tree/riscv-v-clean
I’m interested in your assessment of the opportun…
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RISC-V "V" Vector Extension (shorten as `RVV`) is the instruction extension that introduces vector process capabilities to RISCV.
The staged goal of this issue is to explore the possibility to run…