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After running into some IllegalInstruction exceptions, I found that a number of the PIE instructions on the ESP32-S3 have the wrong instruction format. As an example, the `EE.VADDS.S8.LD.INCP` has wro…
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### Describe the feature request
Wasm Relaxed SIMD includes integer dot product instructions, which will map to VNNI instructions on X86-64 platforms with AVX-VNNI (on ARM maybe SDOT, but I haven't t…
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# Feature or enhancement
### Proposal:
In https://github.com/python/cpython/issues/124951, there has been some initial discussion on improving the performances of `base64` and possibly `{bytearr…
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The WASM [Relaxed SIMD](https://github.com/WebAssembly/relaxed-simd) instructions were stabilized in [Rust v1.82](https://blog.rust-lang.org/2024/10/17/Rust-1.82.0.html#stabilized-apis).
This inclu…
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# Preface
Google [Highway](https://github.com/google/highway) provides a short and concise solution for targeting SIMD on multiple platforms. Although Highway supports dynamic dispatching, the main …
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Hi,
I want to add SIMD instruction support to the spike so I was wondering if I can use the below issue as a reference:
`Support RISC-V p-ext-proposal v0.9 SIMD Data Processing Instructions #57…
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The absence of whole register load/store instructions was already [discussed in the past](https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/203) with the following conclusion:
> The conclus…
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Hi!
I was wondering if there were any specific plan to implement SIMD instructions. I've been playing around with them in the context of the `dense-linear-algebra` library, and they seem to be fund…
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I have a WASM module that uses reference types, but the initialization function (some pure precomputation) doesn't use them. Currently, wizer categorically fails with
```
Error: reference types supp…