riscv-software-src riscv-isa-sim issues

riscv-software-src / riscv-isa-sim

Spike, a RISC-V ISA Simulator

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issues

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spike cache model

#1720 ztjjj9 opened 1 day ago
0
Bump encoding.h for dcsr in debug spec 1.0

#1719 YenHaoChen closed 12 hours ago
0
Implement pointer masking

#1718 YenHaoChen opened 1 day ago
1
Loads to shadow-stack pages are allowed

#1717 aswaterman opened 1 day ago
1
Use input DTB to set all processor + device configurations properly

#1716 abejgonzalez opened 3 days ago
0
Don't print vregs in interactive mode if no V extension exists

#1715 abejgonzalez closed 4 days ago
0
Fix insn interactive command (catch/print trap, use proper access func)

#1714 abejgonzalez closed 4 days ago
0
Add flag to disable ns16550 device

#1713 abejgonzalez closed 5 days ago
3
sbbusyerror model breaks openOCD

#1712 fborisovskii closed 2 days ago
9
Add disassembly for Zfa extension

#1711 aswaterman closed 6 days ago
0
Fix riscv-tests commit for CI

#1710 jerryz123 closed 6 days ago
0
Add insn cmd to interactive debug mode

#1709 abejgonzalez closed 6 days ago
5
Documentation to add an MMIO device as a plugin

#1708 Koceilito opened 1 week ago
1
Reading macro RD behave unexpected

#1707 Lesliehsyu closed 1 week ago
1
doubt with vector masking register instruction

#1706 deepaannnavi opened 1 week ago
0
Fix: Add missing <stdexcept> header for std::logic_error

#1705 rpsene closed 1 week ago
1
Fix C/C++ thread-local linkage differently

#1704 aswaterman closed 1 week ago
0
Fix build of softfloat.h when threads.h is not available.

#1703 dybv-sc closed 1 week ago
2
In isa_parser, move extensionology code before error-checking code

#1702 aswaterman closed 1 week ago
0
Correctly determine vector capability from v/zve/zvl ISA strings, remove --varch

#1701 jerryz123 closed 1 week ago
2
Add Ssdbltrp

#1700 ved-rivos opened 1 week ago
2
Spike behaviour: vector register overlap

#1699 UzairHumayun opened 1 week ago
1
vsetivli yields illegal instruction exception

#1698 Maor545 closed 1 day ago
3
SSTC exception behavior

#1697 JJ-Gaisler closed 1 week ago
3
Legal ISA string option not accepted

#1696 christian-herber-nxp closed 1 week ago
4
Add several BF16 ops to SoftFloat

#1695 aswaterman closed 1 week ago
0
Add a prerequisite for building

#1694 Du-Chao closed 2 weeks ago
0
What time the spike will support the zjpm extension?

#1693 yangye0212 opened 2 weeks ago
0
Dynamic CSR read/write mask

#1692 ved-rivos closed 1 week ago
2
test

#1691 mslijepc closed 2 weeks ago
0
Fix a few compile warnings

#1690 aswaterman closed 1 week ago
0
Make softfloat's rounding mode thread-local

#1689 aswaterman closed 2 weeks ago
5
triggers: implement tcontrol

#1688 YenHaoChen closed 3 weeks ago
0
Separate RV32 and RV64 C instructions into separate files

#1687 aswaterman closed 3 weeks ago
1
issue in counting numbers of instructions

#1686 Sanoj-S-Vijendra closed 3 weeks ago
1
assert failed in vectorUnit.cc from 71line. T&vectorUnit_t::elt(reg_t,reg_t,bool)[with T=long unsigned int; reg_t=long unsigned int]: Assertion '(VLEN>>3)/sizeof(T)>0' failed.

#1685 huihuiei closed 1 month ago
3
Avoid checking ELP before every instruction fetch

#1684 aswaterman closed 1 month ago
1
fatal error: config.h: No such file or directory

#1683 silabs-robin closed 1 month ago
8
Adding Zilsd and Zcmlsd extensions (Load/store pair for RV32)

#1682 christian-herber-nxp closed 2 weeks ago
8
Vector Widening Integer Multiply-Add Instructions - not working

#1681 deepaannnavi closed 1 month ago
2
vmv1r.v instruction's behavior

#1680 EventScheduler closed 1 month ago
1
Updated README with supported Vector Cryptography Extensions

#1679 akifejaz closed 3 weeks ago
3
Require vector extension when attempting vxsat writes

#1678 rbuchner-aril closed 1 month ago
0
vector: Not logging write of reduction instructions when vl = 0

#1677 YenHaoChen closed 1 month ago
0
Facing Issue running Zvbb RVV Cryptography Instructions

#1676 akifejaz closed 1 month ago
3
zicflip: fix [ms]ret behavior

#1675 chihminchao closed 1 month ago
2
Merge upstream

#1674 poemonsense closed 1 month ago
1
for vl=0 does vfredsum need to make vd[0]=vs1[0]?

#1673 xinyuwang-starfive closed 1 month ago
1
Build fails with "error: 'L_tmpnam' was not declared in this scope"

#1672 k138z closed 1 month ago
4
Parse Zve/Zvl to determine RVV settings, instead of --varch

#1671 jerryz123 closed 1 week ago
2