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There is a Platform config Makefile for Xilinx xrt named platforms.mk, but not for Altera opae. When I try to run opae synthesis in DevCloud, it gives missing DPLATFORM_MEMORY_BANKS, DPLATFORM_MEMORY_…
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I want to program the PL part of ZYNQ, but I need a backup of the bitstream. Where can I get it from? If you think about it, LibreSDR is a clone of PlutoSDR, but does that mean that a project for Viva…
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Currently, if you try to use a flip flop with a shaped input, the conversion fails when using `XilinxPlatform`.
Other places in the code might be affected to, I haven't checked that.
To reproduce:…
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**Commit:**
bdfc973d4ed46ff2b3ac5765c2063543b6425a9a
To reproduce the issue:
```
dynamatic> set-dynamatic-path ./dynamatic; set-src ./dynamatic/integration-test/admm/admm.c; set-clock-perio…
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Benchmark:
`symm_float.c`
Script:
```
set-dynamatic-path ./dynamatic; set-src ./dynamatic/integration-test/symm_float/symm_float.c; set-clock-period 5; compile ; write-hdl --hdl veril…
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Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /home/soc_qg/software/vitis2021.2/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --relax --debug …
qgzln updated
3 weeks ago
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It is an enhancement request.
VHDL is supported, but Verilog HDL is not.
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#### Feature request description
Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL.
s as I see it.
Like VHDL, Verilog and SystemVerilog.
## Solution
Implement Major modes for HDLs?
## Alternatives
Develo…
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Hi there,
Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite.
I have no problem synthesizing with [synth_area_top.v](https://github.com/YosysHQ/picorv32/blo…
YapWC updated
6 months ago