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Hello, I have a VHDL module that imports and uses a Verilog library. Even though I setup the project properly, Teros is not able to recognize the verilog libraries and modules.
How can I do that?
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Slowly making replacements for the Qucs Verilog-A Library devices.
1) Modded VCR.sch to get rid of divide by zero if Vin=0 volts. What actual VCR is chosen is TBD.
2) A new mod-amp was created usi…
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**Is your feature request related to a problem? Please describe.**
We are interested in optimizing AST with other graph-based approaches and convert it back to system verilog/verilog module files for…
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We are trying to simulate some simple clockgating blocks that are in verilog. The rest of the design is vhdl.
These seem trivial to convert to VHDL, but the clockgating introduces deltacycle delays o…
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I've found that Synlig, unlike Yosys[^1], generates an incorrect netlist for simple counter if the increment value is an integer literal constant specified in hexadecimal format without optional size …
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After building the hw-cbmc executable from source and trying a simple example to equivalence check C with Verilog, I ran into the issue that assertions never pass once a Verilog module is involved.
…
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Trying to run a gate level verilog test against the HS cell library results in errors because of missing modules:
```
*** These modules were missing:
sky130_fd_sc_hs__u_df_p_pg referenced 6…
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There are times when I need to unit test a mix of VHDL and Verilog.
Including VHDL using Verilog package which references VHDL package for types and constants.
Or Verilog code referencing VHDL packa…
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I think it makes more sense for the common verilog code under [`library`](https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/library) be moved to `common/verilog`.
We have XML stuff under…
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I am exploring a cycle-level (quasi-cycle-accurate) simulator and believe that the rule abstraction of BS fits the task. I want to conduct some trials using BS designs represented as "an elaborated mo…