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During nightly on armv7a9-zynq7000-zedboard on `3cef97a` project hash, one of psh tests failed with error:
```
Exception: 4 #Abort
r0=00024008 r1=00000030 r2=00000ff8 r3=00000048
r4=00024008 …
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**Environment (please complete the following information):**
- Project to build:PYNQ image v3.0
- Petalinux version:2022.1
- HDL branch:2022_R2
- META-ADI branch:2022_R2
- Using meta-adi pet…
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I'm doing this project on ZedBoard. PYNQ linux is OK. But when i do initialize code on jupiter notebook somsing strange happens. What's the difference of PYNQ-Z1 and ZEDboard?
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- Happens occasionally
- Issue firstly discovered on 0a9dfbc (to be investigated whether it can be reproduced using earlier commits)
- For now reproduced only on `u1 zedboard` test unit on CI: ht…
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I tried to build PYNQ image for my Zedboard+AD9361, but occured lots of error, sometimes I can't fix it, it had bothered me for two months. Can u share your image to me? I would be super grateful if y…
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Hello there,
I'm trying to synthesize bigpulp for the ZedBoard. After setting the appropriate paths to Synopsys DesignWare, setting `BOARD` to `zedboard` in `fpga/sourceme.sh` and executing the follo…
k0nze updated
5 years ago
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Hi,
I have a zedboard and used the -f command to program the QSPI. zedboard configured to be in QSPI boot.
openFPGAloader -b zedboard -f design.bit
Jtag frequency : requested 6.00MHz -> real 6…
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Hello,
I am running with the image provided for zedboard_fmcs2, with no modifications and the newest image available here.
My issue is that trying to run the openwifi implementation on the zedboar…
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Hello @asuardi,
running the commands of the steps you provide in Xilinx Vivado design flow example design in tcl command line I'm stucked in the last step when i want to run the test in the zedboard.…
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Hi, got your repository link though the comment you posted on the course 'Function Acceleration on FPGA with Vitis-Part 1: Fundamental'. Just wanted to know that is zedboard fine for implementing the …