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### Description
I'm starting to bring up some software on a Zynq-7000 platform and am running into some issues with unimplemented registers. The first case seems to be when setting up the UART and…
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# Bug Report
## One-Line Summary
Sequence error in ARTIQ 8 that is not expected nor present in ARTIQ 7.
## Issue Details
### Steps to Reproduce
Minimal example experiment code:
…
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I see a few closed issues on this topic indicating that DDR in Zynq (Pynq-Z2) cannot be used because it is not accessible from PL.
When I look at the Zynq7 block design I see 4 AXI 32/64b ports from …
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### Is there an already existing issue for this?
- [X] I have searched the existing issues
### Expected behavior
Computer: WIN11&fastdds 2.14.0
ZYNQ: ubuntu22 arm&fastdds 2.14.0
The computer an…
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### Discussed in https://github.com/konosubakonoakua/blog/discussions/7
Originally posted by **konosubakonoakua** March 12, 2024
# zynq
## Manual
- [Embedded-Design-Tutorials](https://xili…
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im trying to run make -f Makefile.verilator.mk run and i got this error:
../Project/Verilator/obj_dir/VMain_Zynq_Wrapper \
MAX_TEST_CYCLES=100000 \
TEST_CODE=Verification/TestCode/Asm/FP ENABLE_P…
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Hi,
I was wondering if there are any plans for other FPGA ports. I'd mostly be interested in Zedboard and ZCU102.
In the past these ports (and softcores as standalone projects in general) have bee…
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Hi
I have built a sample ofdm application using liquid dsp it works on x86 platform. I am trying to benchmark various ofdm configurations .
./test2_ofdm 512 32
OFDM = 512 , CP =32
total t…
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Hey mate, nice project you've done here, but I plan to use PMOD_CLP on zynq zybo board, does all I need to do is to change the memory location of JA and JB?? or are they exactly the same? I don't know…
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cc @dpetrisko
I'll use this issue to collect benchmarks from Dan. These should be examples where Vivado produces mappings that Dan suspects we can improve upon.