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I observed the following pedantic warnings when running the `golay-24-systematic` source code through a beta version of Oracle's **Parfait** source code analysis tool.
```
Pedantic: Loss of precisio…
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I am following the setup instructions and I am seeing a couple issues.
1. With `make checkout`, I see the following:
```
=====================================
git clone -j 6 --single-branch --re…
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I would like to port this code on Pluto sdr, Few questions in mind.
1. what is the typical Symbol data supported this IP block.
2. Assuming QPSK_3/4 and BW is 5Mhz.
3. Since there is no DVB-s2 Re…
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I am trying to enable secure boot on ARM Zynq board. By studying the boot sequence of the board we found out that it is possible to authenticate with PQC only the partitions starting from the FSBL (si…
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#### Description
The project requires a detailed description of its functionality, including an overview of the `open-hw-cnn` subproject and how it integrates with the Zynq Processing System.
####…
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I'm using ZYNQ 7000 and want to use spinlock to synchronize the two cores (baremetal). The problem is `metal_spinlock_acquire` loops forever.
The code of core0's main.c:
```c
// some includes
…
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It's unclear if the Zynq driver should be used for an R5F FreeRTOS TCP application on the Xilinx MPSoC because of the 32-bit nature of the cores. I wonder if possible to document a compatiability matr…
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## design flow overview
## design flow overview (text version)
```
petalinux-create -t //创建 petalinux 工程
petalinux-config --get-hw-description //导入 hdf/…
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I have a Zybo Zynq 7000. If that is not easily supported by your tools, can you please provide a recommendation for any open source tools which might support it?
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We're seeing an issue with the ALPHA250 where the USB2 port sometimes is useable and sometimes is not, probabilistically, upon power cycling. Software reboots don't appear to matter, but a hard power …