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AdamVerner
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oscilo
school project
GNU General Public License v3.0
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Data reciever
#38
AdamVerner
opened
5 years ago
1
Presentation
#37
AdamVerner
closed
5 years ago
1
Set Sampling speed
#36
AdamVerner
closed
5 years ago
3
add hardware filters to signal
#35
AdamVerner
opened
5 years ago
2
Pc app
#34
AdamVerner
closed
5 years ago
0
Don't scale plot
#33
AdamVerner
opened
5 years ago
0
firmware watchdog
#32
AdamVerner
opened
5 years ago
0
Hdl stable
#31
AdamVerner
closed
5 years ago
2
control app should first request trigger types from device, then display them accordingly
#30
AdamVerner
opened
5 years ago
0
sampler should report that it's done
#29
AdamVerner
closed
5 years ago
2
issue in memory cleaner
#28
AdamVerner
opened
5 years ago
2
allocate offset and it's transmission to current max samle depth
#27
AdamVerner
closed
5 years ago
1
sampler timeout
#26
AdamVerner
closed
5 years ago
1
create quartus headless Makefile
#25
AdamVerner
opened
5 years ago
3
sampler setup returns weird data
#24
AdamVerner
closed
5 years ago
3
Presentation
#23
AdamVerner
closed
5 years ago
1
uart_tx ignores every other packet when trying to transmit fast
#19
AdamVerner
closed
5 years ago
3
reply_cnt counter increases by two instead of one
#18
AdamVerner
closed
5 years ago
3
nefunguje zadnej uart_RX prevodnik
#17
AdamVerner
closed
5 years ago
2
na schematu cyclone desky je spatne TXD A RXD
#16
AdamVerner
closed
5 years ago
5
v piči modul s adcčkem
#15
AdamVerner
closed
5 years ago
2
Pc app
#14
AdamVerner
closed
5 years ago
0
implement better signal management
#13
AdamVerner
opened
5 years ago
1
transfer all init calls
#12
AdamVerner
closed
5 years ago
1
different style of __init__ calling
#11
AdamVerner
closed
5 years ago
4
python installation requirements
#10
AdamVerner
closed
5 years ago
2
verify thtat state watcher works
#8
AdamVerner
closed
5 years ago
1
option to select trigger mode
#7
AdamVerner
closed
5 years ago
1
use OTR signal from ADC
#6
AdamVerner
opened
6 years ago
0
add sources to documentation
#5
AdamVerner
closed
5 years ago
2
useful links
#4
AdamVerner
opened
6 years ago
9
each state_module should have unified structure
#3
AdamVerner
closed
5 years ago
4
transfer ideas from paper to code
#2
AdamVerner
closed
5 years ago
5
test seven segment
#1
AdamVerner
closed
6 years ago
5