Adham-Gohar / Digital-Alarm-Clock

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Digital Alarm Clock ⏰

This project implements a digital alarm clock using Verilog. The design is targeted for the BASYS3 FPGA board and includes several modules for handling different functionalities.

πŸ‘₯ Group Members

πŸ“ Project Structure

πŸ”§ Modules

  1. Clock Divider: Generates slower clock signals from the main clock.
  2. Debouncer: Handles switch debounce.
  3. Digital Alarm Clock: Main module for the digital alarm clock.
  4. Hour and Minute Counter: Manages hour and minute counting.
  5. Multiplexed Output: Controls the 7-segment display multiplexing.
  6. N-Bit Counter: N-bit counter for time counting.
  7. Push Button Detection: Detects push button presses.
  8. Rising Edge Detection: Detects rising edges of signals.
  9. Seven Segment Display: Drives the seven-segment display.
  10. Synchronizer: Synchronizes asynchronous signals.

πŸš€ Getting Started

To get started with this project, clone the repository and navigate to the src directory to view the source files.