This project implements a digital alarm clock using Verilog. The design is targeted for the BASYS3 FPGA board and includes several modules for handling different functionalities.
ASM_Design.png
: ASM design diagram.Block_Diagram.png
: Block diagram of the project.FSM_Design.png
: FSM design diagram.ClockDiv.v
: Clock divider module.Debouncer.v
: Debouncer module.DigitalAlarmClock.v
: Main digital alarm clock module.DigitalAlarmClock_C.v
: Configuration for the digital alarm clock.HourMinCounter.v
: Hour and minute counter module.MultiplexedOutput.v
: Multiplexed output for the 7-segment display.NBitCounter.v
: N-bit counter module.PushButtonDet.v
: Push button detection module.risingEdgeDet.v
: Rising edge detection module.SevenSegment.v
: Seven-segment display module.Synchronizer.v
: Synchronizer module.DigitalAlarmClock_C.xdc
: Constraints file for the digital alarm clock.To get started with this project, clone the repository and navigate to the src
directory to view the source files.