Ajstros / pyripherals

Python solution for communicating with peripheral ICs
GNU General Public License v3.0
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pyripherals is a Python package for communicating with peripheral electronic devices. It has a Register class to keep track of internal registers, but is most useful when used with a FrontPanel compatible Opal Kelly FPGA. With that, pyripherals makes use of the FrontPanel API for Python and Verilog to communicate more easily on common interfaces such as I2C and SPI.

Quick Start

  1. Install with pip

Note that not all of pyripherals will work with Python 3.10

pip install pyripherals

To use an FPGA and peripherals:

  1. Download FrontPanel from OpalKelly

  2. Download Registers.xlsx from the GitHub

  3. Create config.yaml with create_yaml and edit fields as needed

>>> from pyripherals.utils import create_yaml
>>> create_yaml()
YAML created at C:/Users/username/.pyripherals

See Installation Guide for more information.

Documentation

Documentation is hosted on Read the Docs.

Acknowledgements

The FPGA code is dervied from many open-source contributions.

The Python code relies on wonderful open source packages such as:

OpalKelly Module Compatibility.

We have targeted and tested with the XEM7310-A75 module (Xilinx Artix-7). We have not tested but anticipate reasonable portability to other USB 3 OpalKelly modules:

(Approximate) FPGA Block Diagram

This is the block diagram of the top_level_module.bit bitfile