search

AngeloJacobo / ULX3S_FPGA_Camera_Streaming

Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board
MIT License
18 stars 1 forks source link

PLL error #1

Open freetoair opened 9 months ago

freetoair commented 9 months ago

Hi, Angelo

After verification in Icestudio i get this in command output:

iverilog -o hardware.out -D VCD_OUTPUT= -D NO_INCLUDES "C:\Users\n\AppData\Roaming\SPB_Data.icestudio\apio\packages\tools-oss-cad-suite\share\yosys/ecp5/cells_sim.v" main.v main.v:222: error: Unknown module type: EHXPLLL main.v:1645: error: Unknown module type: ODDRX1F main.v:2175: error: Unknown module type: EHXPLLL main.v:2112: error: Unknown module type: ODDRX1F main.v:2113: error: Unknown module type: ODDRX1F main.v:2114: error: Unknown module type: ODDRX1F main.v:2115: error: Unknown module type: ODDRX1F 8 error(s) during elaboration. *** These modules were missing: EHXPLLL referenced 2 times. ODDRX1F referenced 5 times.

scons: *** [hardware.out] Error 8

My board is ULX3S-25F. What is wrong ?

AmarVLSI commented 1 month ago

TRELLIS_IO and OODRXIF files are missing. But OODR is present as an IP but with only clk_in and clk_out signal. In OODR IP Q and sclk signals are missing in Xil;inx Vivado 2023.2 version.