Arlet verilog-6502 issues - Githubissues

Arlet / verilog-6502

A Verilog HDL model of the MOS 6502 CPU

http://c-scape.nl/arlet/fpga/6502/

327 stars 93 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

License?

#6 anders-code opened 1 month ago
1
ALU is a name conflict with GOWIN FPGAs

#5 stacksmith opened 3 months ago
0
Write (WE) active during reset

#4 jesari-git opened 9 months ago
2
Store instruction seems to write to wrong address

#3 ghost closed 9 years ago
9
Verilator build warnings

#2 kallisti5 opened 10 years ago
1
Doesn't build in verilator

#1 kallisti5 closed 10 years ago
3