Capstone2022Team17 / drgbl

Litex/Migen project repository
BSD 2-Clause "Simplified" License
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The FPGA High Bandwith Memory Interfacing and Monitoring Project

DRGBL Logo

Hi! We are BYU Capstone Team 17 (DRGBL)!

We are working on the FPGA High-Bandwidth Memory Interfacing and Monitoring Project!

Video about project

HBM GUI Tutorial

Documentation / Background Info

Our Project Documentation and Background information can be found on our Wiki

We also made a YouTube video detailing our contributions to the LiteX project and our work on High-Bandwidth Memory. You can watch it here: YouTube Link

Contact us

If you have any questions, please reach out at capstone2022.team17@gmail.com.

Overview of Project Implementation

DRGBL Project

Project Requirements

The system requirements can be summarized as follows:

As part of this, we have forked 3 different repositories for this project.

Forked Repositories

Forked LiteX

LiteHBM

Forked litex-boards

What we are working on

We now have working Bandwidth generators and are working on BIOS implementations of their controll. We are also working on data colection and data analysis.

To see a more detailed and individualized tasks check out our project Here.

What is in this Repository