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Codax2000 / fir-cnn-rtl

SystemVerilog for implementing MATLAB neural net onto Xilinx RFSoC.
MIT License
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Need synopsis flow #38

Closed Codax2000 closed 1 year ago

Codax2000 commented 1 year ago

Add synopsis tools from OpenRAM flow, change to have single makefile

Codax2000 commented 1 year ago

RAM from OpenRAM needs to be synthesized properly, ensure timing passing with APR before transitioning to full verilog move. Also, floorplan.tcl needs to be changed to place arrays of RAM so we don't have to do them all by hand.