Optimizing conv_layer to Use Less logical_units

[Codax2000]

Testbench working with 2x5 input, 2x3 kernel

[Codax2000]

Block RAM utilization

[Codax2000]

CLB and LUT utilization. This will likely be lower on our board, since we have DSP slices.

[Codax2000]

Synthesis time:

[Codax2000]

Synthesis and implementation passing in Vivado for convolutional layer:

[Codax2000]

New post-synthesis simulation report: Timing simulation fails hold time (as does synthesis timing report), but there is no clock tree, so wait for post-implementation simulation to sort out hold time violations.

Post-implementation simulation report:

Timing constraints and implementation (for this testbench at least) are fully functional.